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    • 1. 发明申请
    • TRANSPARENT DISPLAY APPARATUS
    • 透明显示设备
    • US20130162616A1
    • 2013-06-27
    • US13462934
    • 2012-05-03
    • Jae Hwa PARKJang-Il KimHyun-Ho KangSwae-Hyun KimYongwoo Hyung
    • Jae Hwa PARKJang-Il KimHyun-Ho KangSwae-Hyun KimYongwoo Hyung
    • G09G5/00G09G3/36
    • G09G3/3648G09G2300/0452G09G2300/08
    • A transparent display apparatus includes a display panel including a plurality of pixels arranged in rows and columns, a plurality of gate lines, a plurality of data lines including first and second data lines, a gate driver, and a data driver. Each of the pixels comprises sub-pixels arranged in a row direction, each gate line is operatively coupled to sub-pixels arranged in a corresponding row, and each first and second data line is operatively coupled to sub-pixels arranged in a corresponding column. The gate driver sequentially applies a gate signal to the pixels through the gate lines. The data driver applies sub-data signals to the sub-pixels through the first data lines, and applies down data signals to the sub-pixels through the second data lines. Each of the down data signals has a voltage level lower than a voltage level of a corresponding sub-data signal.
    • 透明显示装置包括:显示面板,包括排列成行和列的多个像素,多条栅极线,包括第一和第二数据线的多条数据线,栅极驱动器和数据驱动器。 每个像素包括沿行方向布置的子像素,每个栅极线可操作地耦合到布置在相应行中的子像素,并且每个第一和第二数据线可操作地耦合到布置在相应列中的子像素。 栅极驱动器通过栅极线顺序地对像素施加栅极信号。 数据驱动器通过第一数据线将子数据信号施加到子像素,并且通过第二数据线将数据信号施加到子像素。 每个下降数据信号具有低于相应子数据信号的电压电平的电压电平。
    • 4. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • US20080174712A1
    • 2008-07-24
    • US12018885
    • 2008-01-24
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PAKRHyun-Duck SON
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PAKRHyun-Duck SON
    • G02F1/1368
    • G02F1/13624G02F1/136286
    • A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
    • 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。
    • 6. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • US20100270555A1
    • 2010-10-28
    • US12828669
    • 2010-07-01
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PARKHyun-Duck SON
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PARKHyun-Duck SON
    • H01L27/088H01L29/786
    • G02F1/13624G02F1/136286
    • A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
    • 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。
    • 7. 发明授权
    • Thin film transistor array panel
    • 薄膜晶体管阵列面板
    • US07777823B2
    • 2010-08-17
    • US12018885
    • 2008-01-24
    • Jang-Il KimKweon-Sam HongDoo-Hwan YouIn-Ho PakrHyun-Duck Son
    • Jang-Il KimKweon-Sam HongDoo-Hwan YouIn-Ho PakrHyun-Duck Son
    • G02F1/1343
    • G02F1/13624G02F1/136286
    • A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
    • 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。