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1. 发明授权

US06198121B1 Method fabricating a DRAM cell with an area equal to four times the used minimum feature 失效
标题翻译：制造具有等于使用的最小特征的四倍的面积的DRAM单元的方法
公开(公告)号：US06198121B1
公开(公告)日：2001-03-06
申请号：US09022405
申请日：1998-02-12
申请人： JanMye Sung
发明人： JanMye Sung
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.
摘要翻译：已经开发了DRAM单元结构和用于创建DRAM单元结构的制造工艺。 DRAM单元结构消耗的面积通过垂直排列多晶硅字线结构，下层位线结构以及覆盖电容器结构来减少。该过程的特征是在多晶硅字线结构中以及在上层和下面的绝缘体层中产生窄孔。当填充单晶硅时，窄孔将多晶硅字线结构连接到下面的位线结构，以及连接到上覆电容器结构。

2. 发明授权

US06180453B2 Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared 有权
标题翻译：制造具有等于最小使用特征的五倍的面积的DRAM单元的方法
公开(公告)号：US06180453B2
公开(公告)日：2001-01-30
申请号：US09216794
申请日：1998-12-21
申请人： JanMye Sung , Chih-Yuan Lu
发明人： JanMye Sung , Chih-Yuan Lu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10873 , H01L28/91
摘要： A process for fabricating a DRAM cell, with an area equal to five times the minimum feature, squared, (5F2), has been developed. The process features the use of selectively formed, N+ single crystalline, silicon plugs, on underlying source/drain regions. The N+ single crystalline, silicon plugs, epitaxial deposited, are used to connect overlying crown shaped capacitor structures, to underlying source/drain region, as well as to connect a bit line metal structure, to another source/drain region.
摘要翻译：已经开发了制造具有等于最小特征的五倍的面积（5F2）的DRAM单元的工艺。该方法的特征在于在底层的源极/漏极区域上使用选择性形成的N +单晶硅插头。 N +单晶，硅插头，外延沉积，用于将覆盖的冠状电容器结构连接到下层源极/漏极区域，以及将位线金属结构连接到另一个源极/漏极区域。

3. 发明授权

US5821142A Method for forming a capacitor with a multiple pillar structure 失效
标题翻译：一种形成具有多支柱结构的电容器的方法
公开(公告)号：US5821142A
公开(公告)日：1998-10-13
申请号：US629158
申请日：1996-04-08
申请人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
发明人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/92 , H01L28/84 , Y10S438/947 , Y10S438/968
摘要： The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.
摘要翻译：本发明提供一种制造多柱形电容器的方法，该多柱形电容器的尺寸小于光刻工具的分辨率。本发明具有用于形成支柱的两个实施例和用于将导电层图案化成离散底部电极的第三实施例。该方法开始于在第一平坦化层上形成导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔开的透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率的尺寸。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。第三实施例使用两个抗蚀剂层和光掩模移位（偏移）技术在电极之间形成小的空间。最后，在底部电极上形成电容器电介质层和顶部电极，由此完成具有柱状结构的电容器。

4. 发明授权

US5547893A method for fabricating an embedded vertical bipolar transistor and a memory cell 失效
标题翻译：用于制造嵌入式垂直双极晶体管和存储单元的方法
公开(公告)号：US5547893A
公开(公告)日：1996-08-20
申请号：US578923
申请日：1995-12-27
申请人： JanMye Sung
发明人： JanMye Sung
IPC分类号： H01L21/8242 , H01L21/8249 , H01L27/06 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/8249 , H01L27/0623
摘要： The present invention provides a method of simultaneously forming CMOS DRAM cells, CMOS devices, and vertical bipolar transistors on the same chip. The invention utilities a CMOS DRAM process to simultaneously fabricate a vertical bipolar transistor and uses only one additional mask (a base implant mask) compared to forming the DRAM cell alone. Also, to reduce the bipolar collector plug resistance, the process uses a tungsten-plug module where the collector is formed within a field oxide region near the base.
摘要翻译：本发明提供了在同一芯片上同时形成CMOS DRAM单元，CMOS器件和垂直双极晶体管的方法。与仅形成DRAM单元相比，本发明实用于CMOS DRAM工艺以同时制造垂直双极晶体管并且仅使用一个附加掩模（基极注入掩模）。此外，为了降低双极集电极插塞电阻，该方法使用钨 - 塞模块，其中集电极形成在靠近基极的场氧化物区域内。

5. 发明授权

US5753551A Memory cell array with a self-aligned, buried bit line 失效
标题翻译：具有自对准，埋入位线的存储单元阵列
公开(公告)号：US5753551A
公开(公告)日：1998-05-19
申请号：US756088
申请日：1996-11-25
申请人： JanMye Sung
发明人： JanMye Sung
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10808
摘要： A method for forming memory cells, featuring a bit line, embedded in an insulator filled, shallow trench, has been developed. Self-alignment of the buried bit line, to a source and drain region of a transfer gate transistor, is obtained via outdiffusion of a doped polysilicon layer, used as part of the buried bit line, composite layer.
摘要翻译：已经开发了一种形成存储单元的方法，其特征在于嵌入在绝缘体填充的浅沟槽中的位线。通过作为掩埋位线的复合层的一部分的掺杂多晶硅层的扩散，获得掩埋位线到传输栅极晶体管的源极和漏极区域的自对准。

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