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1. 发明授权

US06591318B1 Computer system having reduced number of bus bridge terminals 有权
标题翻译：总线桥接终端数量减少的计算机系统
公开(公告)号：US06591318B1
公开(公告)日：2003-07-08
申请号：US09490771
申请日：2000-01-24
申请人： James W. Meyer , Terry M. Cronin
发明人： James W. Meyer , Terry M. Cronin
IPC分类号： G06F300
CPC分类号： G06F13/4027
摘要： A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.
摘要翻译：系统将BIOS指令从BIOS ROM传输到处理器，用于在系统存储器中执行或存储。 BIOS ROM具有耦合到处理器的地址总线的地址总线和通过IDE总线的数据总线部分耦合到智能驱动电子设备（“IDE”）控制器的数据总线。在操作中，处理器将地址直接应用于BIOS ROM的地址总线，相应的指令通过IDE数据总线和系统控制器耦合到处理器的数据总线。

2. 发明授权

US6073198A System for peer-to-peer mastering over a computer bus 失效
公开(公告)号：US6073198A
公开(公告)日：2000-06-06
申请号：US53392
申请日：1998-03-31
申请人： James W. Meyer , Paul A. Laberge
发明人： James W. Meyer , Paul A. Laberge
IPC分类号： G06F13/40 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4027
摘要： A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

3. 发明授权

US07779212B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
标题翻译：用于通过通信总线从多个源发送数据的方法和装置
公开(公告)号：US07779212B2
公开(公告)日：2010-08-17
申请号：US10688461
申请日：2003-10-17
申请人： James W. Meyer , Kirsten Renick
发明人： James W. Meyer , Kirsten Renick
IPC分类号： G06F12/02
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus.
摘要翻译：在存储器系统中，多个存储器模块通过总线进行通信。每个存储器模块包括集线器和至少一个存储器存储单元。集线器从存储器存储单元接收本地数据，并从一个或多个其他存储器模块接收下行数据。集线器汇集通过总线发送的数据，数据块结构分为多个通道。指示在数据块结构内由第一源（例如，本地或下行数据）在总线上的数据中将发生断点的位置。基于指示，来自第二源（例如，下游或本地数据）的数据被放置在数据块的剩余部分中，从而减少总线上的间隙。

4. 发明授权

US07370122B2 Distributed configuration storage 有权
标题翻译：分布式配置存储
公开(公告)号：US07370122B2
公开(公告)日：2008-05-06
申请号：US11595058
申请日：2006-11-09
申请人： James W. Meyer , Jake Klier
发明人： James W. Meyer , Jake Klier
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F17/5045
摘要： Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.
摘要翻译：提出了用于提供分布式配置存储的系统和方法。配置存储器分为物理上位于使用配置存储的设备的每个设计部分中的分布式配置目标模块。物理位于主机接口附近的分布式配置主模块通过分布式配置总线控制进出每个目标模块的访问。分布式配置存储中每个存储阵列的创建可以使用将每个寄存器规范转换为硬件描述语言代码的脚本工具进行自动化。

5. 发明授权

US06571204B1 Bus modeling language generator 失效
标题翻译：总线建模语言生成器
公开(公告)号：US06571204B1
公开(公告)日：2003-05-27
申请号：US09128704
申请日：1998-08-04
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F300
CPC分类号： G06F17/5022
摘要： The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.
摘要翻译：本发明包括模拟系统装置和方法。本发明可以用于收集描述模拟设备之间期望的数据交换的信息，并且可以帮助生成实现期望的数据交换的仿真模型控制程序。所公开的方法通过与用户交互来接收地址约束并通过生成数据传输指令的集合来产生模拟控制代码。每个数据传输指令包括从地址集合中选择的数据传输地址。所公开的系统具有简化的模拟数据输入系统，其包括用于接收限定数据传输地址值的集合的地址约束信息的装置和用于生成模拟数据传送指令的集合的装置。每个数据传输指令可以包括从数据传送地址值的集合中选择的地址。

6. 发明授权

US06560680B2 System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory 有权
标题翻译：具有集成低延迟存储器的系统控制器，其使用与主存储器物理上不同的不可缓存存储器
公开(公告)号：US06560680B2
公开(公告)日：2003-05-06
申请号：US09994302
申请日：2001-11-26
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F1208
CPC分类号： G06F12/0835 , G06F12/0888
摘要： The present invention relates to a computer system comprising at least one requesting agent, a system controller and a memory subsystem comprising a main memory and a noncacheable subset of main memory physically distinct from the main memory.
摘要翻译：本发明涉及包括至少一个请求代理，系统控制器和存储器子系统的计算机系统，该系统控制器和存储器子系统包括主存储器和与主存储器物理上不同的主存储器的不可缓存子集。

7. 发明授权

US06434720B1 Method of checking data integrity for a RAID 1 system 有权
标题翻译：检查RAID 1系统的数据完整性的方法
公开(公告)号：US06434720B1
公开(公告)日：2002-08-13
申请号：US09251954
申请日：1999-02-17
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： H04L108
CPC分类号： G06F11/1612
摘要： A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.
摘要翻译：一种在计算机系统中检查数据完整性的方法，其包括以下动作：将主数据从主设备发送到主CRC电路; 将次要数据从次级设备发送到次级CRC电路，其中主数据和次级数据同时发送到它们各自的CRC电路; 生成主CRC值; 产生二次CRC值，其中同时产生主CRC值和次CRC值; 以及将主CRC值与次级CRC值进行比较，以便产生比较值。

8. 发明授权

US06223238B1 Method of peer-to-peer mastering over a computer bus 失效
标题翻译：通过计算机总线进行对等母带的方法
公开(公告)号：US06223238B1
公开(公告)日：2001-04-24
申请号：US09053378
申请日：1998-03-31
申请人： James W. Meyer , Paul A. Laberge
发明人： James W. Meyer , Paul A. Laberge
IPC分类号： G06F1314
CPC分类号： G06F13/4027
摘要： A method of communication between requester and target devices in a computer system having a multiple bus architecture. The method supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The method employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The method comprises the act of establishing a handshake with a host master and issuing a request over the host bus. The method further comprises the act of acknowledging the request and transmitting a deferred response to the requester.
摘要翻译：一种具有多总线架构的计算机系统中的请求者和目标设备之间的通信方法。该方法通过主机总线（例如Pentium II或Pentium Pro（P6）总线）支持缓存线读请求的延迟事务。该方法采用主桥通过P6总线发出延迟事务，而不会中断或涉及主处理器。该方法包括与主机主机建立握手并通过主机总线发出请求的动作。该方法还包括确认请求并向请求者发送延迟响应的动作。

9. 发明授权

US6006166A Apparatus for testing a controller with random constraints 失效
标题翻译：用于随机约束测试控制器的装置
公开(公告)号：US6006166A
公开(公告)日：1999-12-21
申请号：US73378
申请日：1998-05-05
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F13/00
CPC分类号： G06F11/261 , G06F2213/3802 , G06F3/0614 , G06F3/0658
摘要： An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel.
摘要翻译：一种用于随机约束测试IDE控制器的装置，所述装置包括：用于模拟所述IDE控制器的IDE控制器模块，其中所述IDE控制器包括至少一个通道和主机接口; 用于产生数据模式并经由主机接口和至少一个信道发送和接收数据模式的控制模块; 耦合到所述控制模块的用于确定所接收的数据模式是否匹配期望值的验证模块; 以及耦合到所述至少一个信道的设备模块，用于接收从所述控制模块发送的数据模式，并经由所述至少一个信道将所述数据模式发送回所述验证模块。

10. 发明授权

US5953352A Method of checking data integrity for a raid 1 system 失效
标题翻译：检查raid 1系统的数据完整性的方法
公开(公告)号：US5953352A
公开(公告)日：1999-09-14
申请号：US880251
申请日：1997-06-23
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F11/16 , G06F11/11
CPC分类号： G06F11/1612
摘要： A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.
摘要翻译：一种在计算机系统中检查数据完整性的方法，其包括以下动作：将主数据从主设备发送到主CRC电路; 将次要数据从次级设备发送到次级CRC电路，其中主数据和次级数据同时发送到它们各自的CRC电路; 生成主CRC值; 产生二次CRC值，其中同时产生主CRC值和次CRC值; 以及将主CRC值与次级CRC值进行比较，以便产生比较值。

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