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1. 发明授权

US07370122B2 Distributed configuration storage 有权
标题翻译：分布式配置存储
公开(公告)号：US07370122B2
公开(公告)日：2008-05-06
申请号：US11595058
申请日：2006-11-09
申请人： James W. Meyer , Jake Klier
发明人： James W. Meyer , Jake Klier
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F17/5045
摘要： Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.
摘要翻译：提出了用于提供分布式配置存储的系统和方法。配置存储器分为物理上位于使用配置存储的设备的每个设计部分中的分布式配置目标模块。物理位于主机接口附近的分布式配置主模块通过分布式配置总线控制进出每个目标模块的访问。分布式配置存储中每个存储阵列的创建可以使用将每个寄存器规范转换为硬件描述语言代码的脚本工具进行自动化。

2. 发明授权

US06591318B1 Computer system having reduced number of bus bridge terminals 有权
标题翻译：总线桥接终端数量减少的计算机系统
公开(公告)号：US06591318B1
公开(公告)日：2003-07-08
申请号：US09490771
申请日：2000-01-24
申请人： James W. Meyer , Terry M. Cronin
发明人： James W. Meyer , Terry M. Cronin
IPC分类号： G06F300
CPC分类号： G06F13/4027
摘要： A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.
摘要翻译：系统将BIOS指令从BIOS ROM传输到处理器，用于在系统存储器中执行或存储。 BIOS ROM具有耦合到处理器的地址总线的地址总线和通过IDE总线的数据总线部分耦合到智能驱动电子设备（“IDE”）控制器的数据总线。在操作中，处理器将地址直接应用于BIOS ROM的地址总线，相应的指令通过IDE数据总线和系统控制器耦合到处理器的数据总线。

3. 发明授权

US6073198A System for peer-to-peer mastering over a computer bus 失效
公开(公告)号：US6073198A
公开(公告)日：2000-06-06
申请号：US53392
申请日：1998-03-31
申请人： James W. Meyer , Paul A. Laberge
发明人： James W. Meyer , Paul A. Laberge
IPC分类号： G06F13/40 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4027
摘要： A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

4. 发明授权

US07120743B2 Arbitration system and method for memory responses in a hub-based memory system 有权
公开(公告)号：US07120743B2
公开(公告)日：2006-10-10
申请号：US10690810
申请日：2003-10-20
申请人： James W. Meyer , Cory Kanski
发明人： James W. Meyer , Cory Kanski
IPC分类号： G06F12/00
CPC分类号： G06F13/1605
摘要： A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

5. 发明授权

US06425056B1 Method for controlling a direct mapped or two way set associative cache memory in a computer system 有权
公开(公告)号：US06425056B1
公开(公告)日：2002-07-23
申请号：US09179236
申请日：1998-10-26
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F1200
摘要： A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators. Thus, both of these control circuits may operate when the cache controller monitors and controls a two-way set-associative cache, while only one of the control circuits will be selectively enabled when the cache controller monitors and controls a direct-mapped cache. The two-state configuration signal may be conveniently provided by a flip-flop or other programmable element whose value is set during computer system initialization routines.

6. 发明授权

US6076180A Method for testing a controller with random constraints 失效
公开(公告)号：US6076180A
公开(公告)日：2000-06-13
申请号：US880351
申请日：1997-06-23
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/221
摘要： A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

7. 发明授权

US6061822A System and method for providing a fast and efficient comparison of cyclic redundancy check (CRC/checks sum) values of two mirrored disks 失效
标题翻译：用于提供两个镜像磁盘的循环冗余校验（CRC /检查和）值的快速有效比较的系统和方法
公开(公告)号：US6061822A
公开(公告)日：2000-05-09
申请号：US880350
申请日：1997-06-23
申请人： James W. Meyer
发明人： James W. Meyer
IPC分类号： G06F5/00 , G06F9/00 , G06F11/00 , G06F11/16 , G06F11/20 , G06F12/00
CPC分类号： G06F11/1612 , G06F11/2056 , G06F11/2064 , G06F11/2066
摘要： An IDE controller having an IDE interface that includes a primary channel for transmitting primary data from a primary device and a secondary channel for transmitting secondary data from a secondary device; a primary CRC circuit for receiving the primary data, performing an operation on the primary data and generating primary CRC values; a secondary CRC circuit for receiving the secondary data, performing an operation on the secondary data and generating secondary CRC values, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; and a compare circuit for comparing the primary CRC values with the secondary CRC values and generating compare values.
摘要翻译：具有IDE接口的IDE控制器，其包括用于从主设备发送主数据的主信道和用于从次设备发送次数据的辅信道; 用于接收主数据的主CRC电路，对主数据执行操作并产生主CRC值; 用于接收次要数据的次级CRC电路，对次要数据执行操作并产生次级CRC值，其中主数据和辅助数据同时发送到它们各自的CRC电路; 以及用于将主CRC值与次级CRC值进行比较并产生比较值的比较电路。

8. 发明授权

US08589643B2 Arbitration system and method for memory responses in a hub-based memory system 失效
标题翻译：基于集线器的存储系统中的内存响应的仲裁系统和方法
公开(公告)号：US08589643B2
公开(公告)日：2013-11-19
申请号：US11318356
申请日：2005-12-22
申请人： James W. Meyer , Cory Kanski
发明人： James W. Meyer , Cory Kanski
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1605
摘要： A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.
摘要翻译：存储器集线器包括存储本地存储器响应的本地队列，传递下游存储器响应的旁路路径和耦合到旁路路径的缓冲队列，其存储来自旁路路径的下行存储器响应。多路复用器耦合到本地队列，缓冲队列和旁路路径，并且响应于控制信号输出来自所选择的一个队列或旁路路径的响应。仲裁控制逻辑耦合到多路复用器和队列，并开发控制信号以控制多路复用器的响应输出。

9. 发明授权

US08327089B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
标题翻译：用于通过通信总线从多个源发送数据的方法和装置
公开(公告)号：US08327089B2
公开(公告)日：2012-12-04
申请号：US13345379
申请日：2012-01-06
申请人： James W. Meyer , Kirsten Renick
发明人： James W. Meyer , Kirsten Renick
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.
摘要翻译：在存储器系统中，多个存储器模块通过总线进行通信。每个存储器模块可以包括集线器和至少一个存储器存储单元。集线器从存储器存储单元接收本地数据，并从一个或多个其他存储器模块接收下行数据。集线器汇集通过总线发送的数据，数据块结构分为多个通道。指示在数据块结构内由第一源（例如，本地或下行数据）在总线上的数据中将发生断点的位置。基于指示，来自第二源（例如，下游或本地数据）的数据被放置在数据块的剩余部分中，从而减少总线上的间隙。公开了附加装置，系统和方法。

10. 发明授权

US08095748B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
公开(公告)号：US08095748B2
公开(公告)日：2012-01-10
申请号：US12847801
申请日：2010-07-30
申请人： James W. Meyer , Kirsten Renick
发明人： James W. Meyer , Kirsten Renick
IPC分类号： G06F13/16
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

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