专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08624658B1 Frequency mixer having parallel mixer cores 有权
标题翻译：具有并联混频器核心的混频器
公开(公告)号：US08624658B1
公开(公告)日：2014-01-07
申请号：US13561529
申请日：2012-07-30
申请人： Theron L. Jones , Richard D. Davis , James Imbornone , Xuejin Wang
发明人： Theron L. Jones , Richard D. Davis , James Imbornone , Xuejin Wang
IPC分类号： G01V3/02
CPC分类号： H03D7/1441 , H03D7/1458 , H03D2200/0023 , H03D2200/0043
摘要： A frequency mixer having parallel mixer cores is described that is configured to heterodyne a signal. In an implementation, the frequency mixer includes a first mixer core and a second mixer core. A first balun is connected to the first mixer core and configured to furnish a LO signal occurring in a first range of frequencies to the first mixer core. The mixer includes a second balun coupled to the second mixer core, and the second balun is configured to furnish a LO signal occurring in a second range of frequencies during a second time interval. The mixer includes a first biasing voltage source that is center tapped to the first balun and a second biasing voltage source is center tapped to the second balun to further prevent operation of the at least substantially non-operational mixer core.
摘要翻译：描述了具有并行混频器核的混频器，其被配置为外差信号。在一个实现中，混频器包括第一混频器核心和第二混频器核心。第一平衡 - 不平衡转换器连接到第一混频器核心并且被配置为向第一混频器核心提供在第一频率范围内出现的LO信号。混频器包括耦合到第二混频器核心的第二平衡 - 不平衡变压器，并且第二平衡 - 不平衡变压器被配置为在第二时间间隔期间提供在第二频率范围内出现的LO信号。混合器包括中心抽头到第一平衡 - 不平衡转换器的第一偏置电压源，并且第二偏压电压源被中心抽头到第二平衡 - 不平衡变换器，以进一步防止至少基本上不可操作的混频器核心的操作。

2. 发明授权

US06396362B1 Compact multilayer BALUN for RF integrated circuits 有权
标题翻译：用于射频集成电路的紧凑型多层BALUN
公开(公告)号：US06396362B1
公开(公告)日：2002-05-28
申请号：US09480032
申请日：2000-01-10
申请人： Jean-Marc Mourant , James Imbornone
发明人： Jean-Marc Mourant , James Imbornone
IPC分类号： H03H742
CPC分类号： H03H7/42 , H01F2021/125
摘要： A compact BALUN transformer comprises a primary and a secondary conductor loop. Each of these loops are disposed in a substantially flat spiral configuration. However, one of these loops, either the primary or the secondary, is preferably disposed in a multi-layer (stacked) configuration. The stacking of at least one of the primary or secondary layers in a multi-layer arrangement provides an increase of impedance in one of the loops. This increased impedance for impedance matching purposes comes with the advantage that parasitic capacitance between primary and secondary layers as would normally be introduced in a multi-layer configuration is absent. In another embodiment of the present invention, both conductor loops are disposed in a multi-layer configuration. Such configurations are particularly useful for 1 to 1 impedance matching conditions and for somewhat lower frequency BALUN circuits.
摘要翻译：紧凑型BALUN变压器包括主导体和次级导体回路。这些环中的每一个都以基本平坦的螺旋结构设置。然而，这些环路中的一个（主要的或次要的）优选地以多层（堆叠）构造设置。多层布置中的至少一个主层或次层的层叠提供了一个环中阻抗的增加。这种用于阻抗匹配目的的增加的阻抗的优点在于，通常不会在多层配置中引入主层和次层之间的寄生电容。在本发明的另一个实施例中，两个导体环路设置成多层结构。这种配置对于1至1阻抗匹配条件和对于稍低频率的BALUN电路特别有用。

3. 发明授权

US06222399B1 Bandgap start-up circuit 有权
标题翻译：带隙启动电路
公开(公告)号：US06222399B1
公开(公告)日：2001-04-24
申请号：US09450567
申请日：1999-11-30
申请人： James Imbornone , Jean-Marc Mourant
发明人： James Imbornone , Jean-Marc Mourant
IPC分类号： G05F110
CPC分类号： G05F3/30 , G05F1/468 , G05F3/247
摘要： A circuit and a method for starting a bandgap circuit which is in a “non-start” mode. The circuit incorporates an inverter circuit with hysterysis and sharp transitions caused by a positive feedback loop. The inverter circuit, which is connected at its input to a bandgap voltage node of the bandgap circuit, activates a switching transistor when voltage (Vbg) at the bandgap voltage node is low and deactivates the switching transistor when Vbg is high. The switching transistor draws current from a critical node of the bandgap circuit, such as the drain of a current mirror PMOS transistor, when it is activated, starting the bandgap circuit.
摘要翻译：用于启动处于“非启动”模式的带隙电路的电路和方法。该电路包含具有由正反馈回路引起的歇斯底里和急剧转变的逆变器电路。当其带隙电压节点处的电压（Vbg）低时，在其输入端连接到带隙电路的带隙电压节点的反相器电路激活开关晶体管，并且当Vbg为高电平时，使开关晶体管停止。开关晶体管在其被激活时从带隙电路的关键节点（例如电流镜PMOS晶体管的漏极）引出电流，启动带隙电路。

4. 发明授权

US6137376A Printed BALUN circuits 有权
标题翻译：印刷BALUN电路
公开(公告)号：US6137376A
公开(公告)日：2000-10-24
申请号：US354376
申请日：1999-07-14
申请人： James Imbornone , Jean-Marc Mourant
发明人： James Imbornone , Jean-Marc Mourant
IPC分类号： H03H7/42
CPC分类号： H03H7/42
摘要： A planar BALUN circuit comprises two separate parallel branches with three capacitive elements. The values of the capacitive elements are selected to provide impedances which first of all enhance balanced current flow and which also impede and reduce unbalanced current flow. The circuit is provided so as to lie substantially in a single plane as a pattern disposed on a printed circuit board together with either certain discrete capacitive elements or with capacitive structures which are also printed on the board. The BALUN circuits of the present invention are particularly useful for circuits operating in the gigahertz range and are particularly useful in light weight devices such as cellular telephones and cellular telephone systems.
摘要翻译：平面BALUN电路包括具有三个电容元件的两个独立的平行分支。选择电容元件的值以提供阻抗，其首先增强平衡电流并且还阻碍和减少不平衡电流。电路被设置为基本上位于单个平面中，作为设置在印刷电路板上的图案以及某些分立的电容元件或者也印刷在电路板上的电容结构。本发明的BALUN电路对于在千兆赫兹范围内工作的电路特别有用，并且在诸如蜂窝电话和蜂窝电话系统的轻量级设备中特别有用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式