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1. 发明授权

US06532533B1 Input/output system with mask register bit control of memory mapped access to individual input/output pins 有权
标题翻译：输入/输出系统具有掩码寄存器位控制，存储器映射访问各个输入/输出引脚
公开(公告)号：US06532533B1
公开(公告)日：2003-03-11
申请号：US09450889
申请日：1999-11-29
申请人： Amarjit S. Bhandal , Graham Short , Richard Simpson
发明人： Amarjit S. Bhandal , Graham Short , Richard Simpson
IPC分类号： G06F1320
CPC分类号： G06F9/30018 , G06F9/30101
摘要： A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56) has bits corresponding to each pin for driving the signal on the pin (52) to a desired value. An output enable register (58) controls output buffers (62) coupled between the output register (56) and the pins (52). A plurality of mask registers (60) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register (56), the data output register (58) and the output enable register (60) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register (60). Logic (50) accesses the data registers in view of the state of the associated mask register (60).
摘要翻译：处理装置（10）提供通用的输入/输出引脚（52），以供软件程序根据需要使用。数据输入寄存器（54）具有对应于每个引脚（52）的位，用于存储引脚上的信号值。数据输出寄存器（56）具有与每个引脚相对应的位，用于将引脚（52）上的信号驱动到期望值。输出使能寄存器（58）控制耦合在输出寄存器（56）和引脚（52）之间的输出缓冲器（62）。多个掩模寄存器（60）可以被单独设置以限定与掩模相关联的引脚的集合。通过多个地址访问数据寄存器，数据输入寄存器（56），数据输出寄存器（58）和输出使能寄存器（60）中的每一个，其中地址指定正被访问的数据寄存器和相关联的屏蔽寄存器（60）。鉴于相关屏蔽寄存器（60）的状态，逻辑（50）访问数据寄存器。

2. 发明授权

US5269021A Multiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run time 失效
标题翻译：使用部分链接的动态加载模块的图形处理器子系统的多处理器软件接口，这些模块在运行时被下载并完全链接
公开(公告)号：US5269021A
公开(公告)日：1993-12-07
申请号：US420409
申请日：1989-10-12
申请人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
发明人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
IPC分类号： G06F9/40 , G06F9/445 , G06F15/16
CPC分类号： G06F9/4425 , G06F9/44521
摘要： An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.
摘要翻译：一种与多处理器计算机系统一起使用的接口，具有主处理器系统和图形处理器系统。该接口允许在主机系统或另一个系统上开发扩展功能，并随后加载到图形处理器系统。该接口包括驻留在主机系统侧和图形系统侧的软件，其在运行时操作以允许从主机上运行的主程序调用该功能。该函数的参数传递给图形系统，以使该函数由图形处理器执行。

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