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1. 发明申请

US20120233360A1 Unified DMA 有权
标题翻译：统一DMA
公开(公告)号：US20120233360A1
公开(公告)日：2012-09-13
申请号：US13474373
申请日：2012-05-17
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

2. 发明授权

US08176257B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US08176257B2
公开(公告)日：2012-05-08
申请号：US13087974
申请日：2011-04-15
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

3. 发明授权

US07970970B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址开关，每个代理队列较浅
公开(公告)号：US07970970B2
公开(公告)日：2011-06-28
申请号：US12787865
申请日：2010-05-26
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

4. 发明授权

US07680963B2 DMA controller configured to process control descriptors and transfer descriptors 有权
标题翻译： DMA控制器配置为处理控制描述符和传输描述符
公开(公告)号：US07680963B2
公开(公告)日：2010-03-16
申请号：US11682065
申请日：2007-03-05
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

5. 发明授权

US07349399B1 Method and apparatus for out-of-order processing of packets using linked lists 有权
标题翻译：使用链表对数据包进行无序处理的方法和装置
公开(公告)号：US07349399B1
公开(公告)日：2008-03-25
申请号：US10327555
申请日：2002-12-20
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

6. 发明授权

US07269682B2 Segmented interconnect for connecting multiple agents in a system 有权
标题翻译：用于连接系统中多个代理的分段互连
公开(公告)号：US07269682B2
公开(公告)日：2007-09-11
申请号：US11201573
申请日：2005-08-11
申请人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
发明人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00 , G06F13/36 , H04L12/00 , H04L12/12
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

7. 发明申请

US20070038796A1 Partially populated, hierarchical crossbar 有权
标题翻译：部分居住，分层横梁
公开(公告)号：US20070038796A1
公开(公告)日：2007-02-15
申请号：US11201573
申请日：2005-08-11
申请人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
发明人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

8. 发明授权

US5793260A Current controlled oscillator with voltage independent capacitance 失效
标题翻译：具有电压独立电容的电流控制振荡器
公开(公告)号：US5793260A
公开(公告)日：1998-08-11
申请号：US641101
申请日：1996-04-26
申请人： Marwan A. Fawal , Burton B. Lo , Ruchi Wadhawan
发明人： Marwan A. Fawal , Burton B. Lo , Ruchi Wadhawan
IPC分类号： H01L21/822 , H01L27/04 , H03K3/0231 , H01G9/048 , H03L7/085
CPC分类号： H03K3/0231
摘要： A current-controlled oscillator with first and second differential comparators (640, 840) serving as inputs, first and second voltage independent multi-layered integrated capacitors (600, 800) corresponding to the first and second comparators (640, 840), and a RS latch (700) for switching operation between the two comparators (640, 840) thereby achieving oscillation. The multi-layered integrated capacitors (600, 800) are designed to provide voltage independent capacitance.
摘要翻译：具有用作输入的第一和第二差分比较器（640,840）的电流控制振荡器，对应于第一和第二比较器（640,840）的第一和第二电压无关多层集成电容器（600,800），以及 RS锁存器（700），用于在两个比较器（640,840）之间切换操作，从而实现振荡。多层集成电容器（600,800）被设计成提供电压独立的电容。

9. 发明授权

US08959270B2 Interrupt distribution scheme 有权
标题翻译：中断分配方案
公开(公告)号：US08959270B2
公开(公告)日：2015-02-17
申请号：US12962146
申请日：2010-12-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
发明人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

10. 发明授权

US08417844B2 DMA controller which performs DMA assist for one peripheral interface controller and DMA operation for another peripheral interface controller 有权
标题翻译： DMA控制器为一个外设接口控制器执行DMA辅助，并为另一个外设接口控制器执行DMA操作
公开(公告)号：US08417844B2
公开(公告)日：2013-04-09
申请号：US13474373
申请日：2012-05-17
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

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