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    • 8. 发明申请
    • NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION
    • 非易失性存储器件及其相关操作方法
    • US20120331210A1
    • 2012-12-27
    • US13526794
    • 2012-06-19
    • JAEYONG JEONGJU SEOK LEE
    • JAEYONG JEONGJU SEOK LEE
    • G06F12/02
    • G11C16/26G11C11/5642G11C16/24G11C16/3454
    • A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.
    • 非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列,连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。 控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元,并且读取对应于偶数和奇数列之一的存储器单元 的第二读取模式。 在第一读取模式下执行感测操作至少两次,并且在第二读取模式中执行一次感测操作。