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1. 发明授权

US09406871B2 Magnetoresistive element and method of manufacturing the same 有权
公开(公告)号：US09406871B2
公开(公告)日：2016-08-02
申请号：US14807267
申请日：2015-07-23
申请人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
发明人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
IPC分类号： H01L43/00 , H01L43/02 , H01L27/22 , H01L43/08 , H01L43/12 , H01L43/10
CPC分类号： H01L43/02 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

2. 发明申请

US20150069558A1 MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：磁记忆及其制造方法
公开(公告)号：US20150069558A1
公开(公告)日：2015-03-12
申请号：US14203249
申请日：2014-03-10
申请人： Masahiko NAKAYAMA , Tadashi KAI , Masaru TOKO , Hiroaki YODA , Hyung Suk LEE , Jae Geun OH , Choon Kun RYU , Min Suk LEE
发明人： Masahiko NAKAYAMA , Tadashi KAI , Masaru TOKO , Hiroaki YODA , Hyung Suk LEE , Jae Geun OH , Choon Kun RYU , Min Suk LEE
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/02 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/5607 , H01L27/222 , H01L27/228 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/04
摘要： According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.
摘要翻译：根据一个实施例，公开了一种磁存储器。该存储器包括一个包含第一金属材料的导电层，在该导电层上方的层叠体，并且包括一个第一磁化膜，该第一磁化膜含有第二金属材料，第二磁化膜和第一磁化膜与第二磁化膜之间的隧道势垒层磁化膜和层叠体的侧面上的绝缘层，并且含有第一金属材料的氧化物。第一磁化膜和/或第二磁化膜包括位于中心部分的第一区域和位于边缘部分中并且包含As，P，Ge，Ga，Sb，In，N，Ar，He的第二区域， F，Cl，Br，I，Si，B，C，O，Zr，Tb，S，Se或Ti。

3. 发明申请

US20120007258A1 SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有侧面结构的半导体器件及其制造方法
公开(公告)号：US20120007258A1
公开(公告)日：2012-01-12
申请号：US12939677
申请日：2010-11-04
申请人： Jae-Geun Oh , Seung-Joon Jeon , Jin-Ku Lee , Mi-Ri Lee , Bong-Seok Jeon
发明人： Jae-Geun Oh , Seung-Joon Jeon , Jin-Ku Lee , Mi-Ri Lee , Bong-Seok Jeon
IPC分类号： H01L23/522 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/743 , H01L27/10876 , H01L27/10885 , H01L29/1608 , H01L29/165 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.
摘要翻译：一种制造半导体器件的方法包括：形成多个通过沟槽与另一个隔离的主体，并且每个都包括具有暴露于沟槽的侧壁的扩散阻挡区域，形成填充沟槽的掺杂层间隙，形成侧壁通过退火掺杂层而在扩散阻挡区域的暴露的侧壁处形成连接，并且形成与侧壁接合部连接以填充沟槽的导电线。

4. 发明授权

US07919373B2 Method for doping polysilicon and method for fabricating a dual poly gate using the same 失效
标题翻译：掺杂多晶硅的方法及其制造方法
公开(公告)号：US07919373B2
公开(公告)日：2011-04-05
申请号：US12165182
申请日：2008-06-30
申请人： Jin-Ku Lee , Jae-Geun Oh , Sun-Hwan Hwang
发明人： Jin-Ku Lee , Jae-Geun Oh , Sun-Hwan Hwang
IPC分类号： H01L21/336 , H01L21/00 , H01L21/20
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/02675 , H01L27/10876 , H01L27/10894
摘要： A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced.
摘要翻译：掺杂多晶硅的方法改善了等离子体掺杂期间的掺杂分布，并且包括使用两个单独的操作形成硅层。在形成第一硅层之后，进行热退火以使第一硅层结晶，使得在等离子体掺杂期间根据内层的深度的掺杂浓度的均匀性得到改善。此外，在多晶硅层和栅极氧化物层之间的界面处的掺杂浓度增加。由于多晶硅层中的掺杂浓度的增加，副产物沉积层被还原，其形成在多晶硅层的表面上。结果，减少了在掺杂期间使用的离子注入阻挡层的去除和清洁引起的掺杂剂损耗。

5. 发明授权

US07687361B2 Method of fabricating a transistor having a triple channel in a memory device 有权
标题翻译：在存储器件中制造具有三通道的晶体管的方法
公开(公告)号：US07687361B2
公开(公告)日：2010-03-30
申请号：US11155833
申请日：2005-06-17
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/66795
摘要： Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.
摘要翻译：公开了一种制造存储器件的晶体管的方法，该方法能够防止在形成低电阻栅电极时产生空隙。该方法包括以下步骤：通过蚀刻半导体衬底形成有源区，在半导体衬底中形成场氧化物层，并通过蚀刻场氧化物层形成凹陷。栅极绝缘层沿有源区的上表面和有源区的暴露部分形成。栅极电极形成在场氧化物层上，使得栅极电极延伸跨过有源区域的上部，同时与沟道区域和凹部重叠。待图案化的第一导电层具有相同的厚度，因此在不形成空隙的情况下容易地制造低电阻栅电极。

6. 发明申请

US20080096355A1 TRANSISTOR STRUCTURE OF MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US20080096355A1
公开(公告)日：2008-04-24
申请号：US11962100
申请日：2007-12-21
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

7. 发明授权

US07029999B2 Method for fabricating transistor with polymetal gate electrode 失效
标题翻译：用多金属栅电极制造晶体管的方法
公开(公告)号：US07029999B2
公开(公告)日：2006-04-18
申请号：US10750084
申请日：2003-12-30
申请人： Kwan-Yong Lim , Byung-Seop Hong , Heung-Jae Cho , Jung-Ho Lee , Jae-Geun Oh , Yong-Soo Kim , Se-Aug Jang , Hong-Seon Yang , Hyun-Chul Sohn
发明人： Kwan-Yong Lim , Byung-Seop Hong , Heung-Jae Cho , Jung-Ho Lee , Jae-Geun Oh , Yong-Soo Kim , Se-Aug Jang , Hong-Seon Yang , Hyun-Chul Sohn
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28061 , H01L21/28247
摘要： The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.
摘要翻译：本发明涉及一种制造具有多金属栅电极结构的晶体管的方法。该方法包括以下步骤：在衬底上形成栅极绝缘层; 在所述栅极绝缘层上形成图案化的栅极堆叠结构，其中所述图案化的堆叠结构包括作为底层的多晶硅层和作为上层的金属层; 沿着包含图案化的栅叠层结构的轮廓形成氧化硅基覆盖层，并在预定温度下在栅极绝缘层上形成防止金属层氧化的氧化硅基覆盖层; 并进行栅极再氧化处理。

8. 发明申请

US20050019992A1 Method for manufacturing gate electrode for use in semiconductor device 审中-公开
标题翻译：制造用于半导体器件的栅电极的方法
公开(公告)号：US20050019992A1
公开(公告)日：2005-01-27
申请号：US10739653
申请日：2003-12-17
申请人： Byung-Seop Hong , Jae-Geun Oh
发明人： Byung-Seop Hong , Jae-Geun Oh
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8242 , H01L21/00 , H01L21/84
CPC分类号： H01L21/28061 , H01L27/10873
摘要： A method for manufacturing an enhanced tungsten gate electrode for use in a semiconductor device is disclosed to adopt a selective oxidation process in an inert gas or a nitrogen gas ambient. The method includes the steps of: preparing a semiconductor substrate obtained by a predetermined process; forming a gate oxide layer on the semiconductor substrate; forming a tungsten polymetal gate electrode including a polysilicon and a tungsten formed on the gate oxide layer in sequence; and carrying out a selective oxidation process in an ambient of a source gas containing hydrogen gas (H2) diluted with an inert gas or a nitrogen gas for forming a selective oxide on sidewalls of the polysilicon.
摘要翻译：公开了一种制造用于半导体器件的增强钨栅极的方法，以在惰性气体或氮气环境中采用选择性氧化工艺。该方法包括以下步骤：制备通过预定工艺获得的半导体衬底; 在半导体衬底上形成栅极氧化层; 在栅极氧化物层上依次形成包括多晶硅和钨的钨多金属栅电极; 并在含有用惰性气体或氮气稀释的氢气（H2）的源气体的环境中进行选择性氧化处理，以在多晶硅的侧壁上形成选择性氧化物。

9. 发明申请

US20120302047A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PARTIALLY OPEN SIDEWALL 审中-公开
标题翻译：用于制造具有部分开口的半导体器件的方法
公开(公告)号：US20120302047A1
公开(公告)日：2012-11-29
申请号：US13230931
申请日：2011-09-13
申请人： Mi-Ri LEE , Jae-Geun Oh , Seung-Joon Jeon , Jin-Ku Lee , Bong-Seok Jeon
发明人： Mi-Ri LEE , Jae-Geun Oh , Seung-Joon Jeon , Jin-Ku Lee , Bong-Seok Jeon
IPC分类号： H01L21/265
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/66666 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure.
摘要翻译：一种半导体器件的制造方法，其特征在于，在所述第一面之间形成具有位于第二面以上的高度的第一表面的结构，在所述结构上形成第一硅层，对所述第一硅层进行倾斜离子注入工序以形成晶体区域和非晶区域，在非晶区域上形成第二硅层，去除第二硅层和第一硅层，直到第二表面的一部分露出，从而形成蚀刻阻挡层，并使用蚀刻阻挡层以形成暴露结构的侧壁的一部分的开放部分。

10. 发明申请

US20110212591A1 METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件晶体管的制造方法
公开(公告)号：US20110212591A1
公开(公告)日：2011-09-01
申请号：US12964562
申请日：2010-12-09
申请人： Jae-Geun OH , Young-Ho Lee , Jin-Ku Lee , Mi-Ri Lee
发明人： Jae-Geun OH , Young-Ho Lee , Jin-Ku Lee , Mi-Ri Lee
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/268 , H01L21/2686 , H01L21/28061 , H01L29/66575
摘要： A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region.
摘要翻译：一种制造半导体器件的晶体管的方法包括：在衬底上形成栅极图案; 通过在所述栅极图案的相对侧上对所述衬底进行注入工艺来形成结区域; 在大约770℃至850℃的温度下在接合区域进行固相外延（SPE）工艺; 并在接合区域上进行快速热退火（RTA）处理。

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