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1. 发明授权

US09024654B2 System and method to actively drive the common mode voltage of a receiver termination network 有权
标题翻译：系统和方法来主动驱动接收机终端网络的共模电压
公开(公告)号：US09024654B2
公开(公告)日：2015-05-05
申请号：US13615802
申请日：2012-09-14
申请人： Robert Thelen , Michael Farmer , Jade Kizer
发明人： Robert Thelen , Michael Farmer , Jade Kizer
IPC分类号： H03K19/003 , H04L25/02
CPC分类号： H04L25/0276
摘要： An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.
摘要翻译：用于差分接收器的有源终端电路包括被配置为接收差分信号的第一分量的第一接收器元件，被配置为接收差分信号的第二分量的第二接收器元件，被配置为接收差分信号的共模测量元件并生成表示差分信号的平均值的发送共模信号（Vcm）以及接收机（RX）共模信号节点。终端电路还包括被配置为接收发射共模信号（Vcm）并且向接收器共模信号节点提供输出的有源元件，该输出被配置为将接收器共模信号节点处的信号的值驱动到发送共模信号（Vcm）的值，以及耦合到与有源元件并联的接收器共模信号节点的电容元件。

2. 发明授权

US08649460B2 Techniques for multi-wire encoding with an embedded clock 有权
标题翻译：使用嵌入式时钟进行多线编码的技术
公开(公告)号：US08649460B2
公开(公告)日：2014-02-11
申请号：US12663230
申请日：2008-06-04
申请人： Frederick Ware , Jade Kizer
发明人： Frederick Ware , Jade Kizer
IPC分类号： H04L27/00
CPC分类号： H03M5/16 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K3/356026 , H03K19/01855 , H03M5/20 , H04L25/0272 , H04L25/4906 , H04L25/4917
摘要： Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
摘要翻译：公开了一种具有嵌入式时钟的多线编码技术。在一个特定的示例性实施例中，这些技术可以被实现为发射器部件。发射机组件可以包括至少一个编码器模块以产生一组符号，每个符号由一组线路上的信号电平的组合表示。发射机组件还可以包括至少一个信令模块，用于根据传输时钟在一组线路上传输一个或多个符号。发射机组件可以另外包括控制逻辑，以将该组符号的第一和第二子集的发射限制到发射时钟的时钟周期的相应第一和第二部分，使得在该组线中的至少两个之间的信号差分表现出与发送时钟频率相同的开关行为。

3. 发明申请

US20060059392A1 Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER) 有权
标题翻译：用于从误码率（BER）估计随机抖动（RJ）和确定性抖动（DJ）的方法和装置
公开(公告)号：US20060059392A1
公开(公告)日：2006-03-16
申请号：US10939028
申请日：2004-09-10
申请人： Jade Kizer , Christopher Madden
发明人： Jade Kizer , Christopher Madden
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G01R31/31709 , G01R31/3171 , G11C29/022
摘要： An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled. In an embodiment of the present invention, the first and second counters are logarithmic counters that include overflow protection. The counter values are output to a processing device to perform the BER calculation in an embodiment of the present invention. A plurality of BER values is then obtained for corresponding offsets. A subset of the plurality of BER values corresponding to the plurality of offsets is selected. An inverse of the standard normal cumulative distribution (NormSlnv) function for respective BER values is calculated. Two linear fits on the transformed BER values and offsets are performed to obtain the x-intercepts that correspond to a DJ component and the slopes corresponding to a RJ component. The DJ and RJ components are used with the Fibre Channel jitter model equation to predict BER as a function of transition density and offset value.
摘要翻译：一种装置和方法提供了对诸如处理器和存储器装置的IC之间的接口的BER的预测，而不使用特殊的测试设备。已知的数据模式或PRBS被发送到接收机，接收机将接收到的数据值与期望的数据值进行比较，以确定在本发明的实施例中是否发生了位错误。数据眼的中心和数据眼的边缘被采样（过采样），以便确定在本发明的替代实施例中是否发生位错误。第一计数器用于对采样的总位数进行计数，第二计数器用于对所采样总位数中发生的错误数进行计数。在本发明的实施例中，第一和第二计数器是包括溢出保护的对数计数器。在本发明的实施例中，计数器值被输出到处理装置以执行BER计算。然后对于相应的偏移获得多个BER值。选择与多个偏移对应的多个BER值的子集。计算相应BER值的标准正态累积分布（NormSlnv）函数的倒数。执行对经变换的BER值和偏移的两个线性拟合以获得对应于DJ分量的x截距和对应于RJ分量的斜率。 DJ和RJ组件与光纤通道抖动模型方程一起用于预测BER作为转换密度和偏移值的函数。

4. 发明申请

US20050206419A1 Locked loop with dual rail regulation 有权
标题翻译：锁定环路，双轨调节
公开(公告)号：US20050206419A1
公开(公告)日：2005-09-22
申请号：US11130682
申请日：2005-05-17
申请人： Jade Kizer , Benedict Lau
发明人： Jade Kizer , Benedict Lau
IPC分类号： G06F1/10 , H03L7/07 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/07 , H03L7/0814
摘要： An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply voltages according to a phase difference between a selected pair of the reference clock signals.
摘要翻译：具有双轨限制参考回路的装置。参考回路包括由上和下电源电压供电以产生多个参考时钟信号的延迟电路，以及电压调节电路，用于根据所选择的一对参考时钟信号之间的相位差来调节上下电源电压。

5. 发明申请

US20050046454A1 Phase synchronization for wide area integrated circuits 有权
标题翻译：广域集成电路的相位同步
公开(公告)号：US20050046454A1
公开(公告)日：2005-03-03
申请号：US10963698
申请日：2004-10-13
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G06F1/10 , H03L7/00 , H03L7/06
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

6. 发明授权

US06798243B1 Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage 有权
标题翻译：输入接收电路从高外部电压到低内部电源电压的装置和方法
公开(公告)号：US06798243B1
公开(公告)日：2004-09-28
申请号：US10629167
申请日：2003-07-28
申请人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
发明人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
IPC分类号： H03K190175
CPC分类号： H03K19/018528
摘要： A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.
摘要翻译：公开了用于电平移位输入信号的电路和方法，其提供输入信号的电平移位，其中外部电压电平大于信号的内部电压。在本发明中，将输入信号与参考信号进行比较，以产生反映输入信号的逻辑电平的差分电流信号。差分电流信号通过从外部电压电平工作的一对电流镜反射，以驱动一对电阻负载。每个电阻负载与内部电源电压和接地电压之间的电流吸收器串联耦合。结果，即使当内部电源电压小于晶体管阈值电压的两倍时，也可以接收输入信号并进行电平移位，而不会对接收到的信号引入显着的失真。

7. 发明授权

US06636098B1 Differential integrator and related circuitry 失效
标题翻译：差分积分器及相关电路
公开(公告)号：US06636098B1
公开(公告)日：2003-10-21
申请号：US10002007
申请日：2001-12-05
申请人： Jade Kizer
发明人： Jade Kizer
IPC分类号： G06F764
CPC分类号： H03K5/1565 , H03F3/45192 , H03F3/4565 , H03F3/45654 , H03F3/45659 , H03F2203/45028 , H03F2203/45352 , H03F2203/45356 , H03F2203/45466 , H03F2203/45642
摘要： An improved differential integrator and related circuitry is disclosed. In one exemplary embodiment, the improved differential integrator comprises an integrating gain boosted cascode circuit for receiving an input signal having a first locking time and for generating an output signal having a second locking time, wherein the second locking time being delayed by a predetermined amount from the first locking time. The improved differential integrator may also comprise a multi-node common-mode feedback circuit, and a dynamic cascode common-mode feedback circuit. The integrating gain boosted cascode circuit may include a gain boosted cascode structure and a capacitor compensation structure. The multi-node common-mode feedback circuit may include a folded cascode circuit. The dynamic cascode common-mode feedback circuit may include a cascode circuit that uses common-mode feedback.
摘要翻译：公开了一种改进的差分积分器和相关电路。在一个示例性实施例中，改进的差分积分器包括用于接收具有第一锁定时间的输入信号并用于产生具有第二锁定时间的输出信号的积分增益升压共源共栅电路，其中第二锁定时间被延迟预定量第一个锁定时间。改进的差分积分器还可以包括多节点共模反馈电路和动态共源共模共模反馈电路。积分增益升压共源共栅电路可以包括增益升压共源共栅结构和电容器补偿结构。多节点共模反馈电路可以包括折叠共源共栅电路。动态级联共模反馈电路可以包括使用共模反馈的共源共栅电路。

8. 发明申请

US20140079106A1 System And Method To Actively Drive The Common Mode Voltage Of A Receiver Termination Network 有权
标题翻译：系统和方法来主动驱动接收机终端网络的共模电压
公开(公告)号：US20140079106A1
公开(公告)日：2014-03-20
申请号：US13615802
申请日：2012-09-14
申请人： Robert Thelen , Michael Farmer , Jade Kizer
发明人： Robert Thelen , Michael Farmer , Jade Kizer
IPC分类号： H04B17/00
CPC分类号： H04L25/0276
摘要： An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.
摘要翻译：用于差分接收器的有源终端电路包括被配置为接收差分信号的第一分量的第一接收器元件，被配置为接收差分信号的第二分量的第二接收器元件，被配置为接收差分信号的共模测量元件并生成表示差分信号的平均值的发送共模信号（Vcm）以及接收机（RX）共模信号节点。终端电路还包括被配置为接收发射共模信号（Vcm）并且向接收器共模信号节点提供输出的有源元件，该输出被配置为将接收器共模信号节点处的信号的值驱动到发送共模信号（Vcm）的值，以及耦合到与有源元件并联的接收器共模信号节点的电容元件。

9. 发明申请

US20050030071A1 PHASE SYNCHRONIZATION FOR WIDE AREA INTEGRATED CIRCUITS 有权
标题翻译：宽区域集成电路的相位同步
公开(公告)号：US20050030071A1
公开(公告)日：2005-02-10
申请号：US10633831
申请日：2003-08-04
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G06F1/10 , H03L7/00 , H03L7/06
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

10. 发明授权

US06819137B1 Technique for voltage level shifting in input circuitry 失效
标题翻译：输入电路中电压电平转换的技术
公开(公告)号：US06819137B1
公开(公告)日：2004-11-16
申请号：US10237963
申请日：2002-09-10
申请人： Yueyong Wang , Jade Kizer , Chanh Tran , Benedict Lau
发明人： Yueyong Wang , Jade Kizer , Chanh Tran , Benedict Lau
IPC分类号： H03K19094
CPC分类号： H03K19/018528
摘要： A technique for voltage level shifting in input circuitry is disclosed. In one exemplary embodiment, the technique may be realized as a method for voltage level shifting input signals. This method may comprise receiving first and second input signals having first and second voltage levels, respectively, and then differentially amplifying the first and second input signals so as to generate first and second amplified voltage signals having first and second amplified voltage levels, respectively, wherein the first and second amplified voltage signals are substantially complementary. This method may then comprise reducing the first and second amplified voltage levels of the first and second amplified voltage signals so as to generate first and second level shifted amplified voltage signals having first and second level shifted amplified voltage levels, respectively.
摘要翻译：公开了一种用于输入电路中的电压电平移位的技术。在一个示例性实施例中，该技术可以被实现为用于电压电平移位输入信号的方法。该方法可以包括分别接收具有第一和第二电压电平的第一和第二输入信号，然后差分放大第一和第二输入信号，以分别产生具有第一和第二放大电压电平的第一和第二放大电压信号，其中第一和第二放大电压信号是基本互补的。该方法可以包括减小第一和第二放大电压信号的第一和第二放大电压电平，以分别产生具有第一和第二电平移位放大电压电平的第一和第二电平移位放大电压信号。

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