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1. 发明授权

US08649460B2 Techniques for multi-wire encoding with an embedded clock 有权
标题翻译：使用嵌入式时钟进行多线编码的技术
公开(公告)号：US08649460B2
公开(公告)日：2014-02-11
申请号：US12663230
申请日：2008-06-04
申请人： Frederick Ware , Jade Kizer
发明人： Frederick Ware , Jade Kizer
IPC分类号： H04L27/00
CPC分类号： H03M5/16 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K3/356026 , H03K19/01855 , H03M5/20 , H04L25/0272 , H04L25/4906 , H04L25/4917
摘要： Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
摘要翻译：公开了一种具有嵌入式时钟的多线编码技术。在一个特定的示例性实施例中，这些技术可以被实现为发射器部件。发射机组件可以包括至少一个编码器模块以产生一组符号，每个符号由一组线路上的信号电平的组合表示。发射机组件还可以包括至少一个信令模块，用于根据传输时钟在一组线路上传输一个或多个符号。发射机组件可以另外包括控制逻辑，以将该组符号的第一和第二子集的发射限制到发射时钟的时钟周期的相应第一和第二部分，使得在该组线中的至少两个之间的信号差分表现出与发送时钟频率相同的开关行为。

2. 发明申请

US20100215118A1 TECHNIQUES FOR MULTI-WIRE ENCODING WITH AN EMBEDDED CLOCK 有权
标题翻译：用嵌入式时钟进行多线编码的技术
公开(公告)号：US20100215118A1
公开(公告)日：2010-08-26
申请号：US12663230
申请日：2008-06-04
申请人： Frederick Ware , Jade Kizer
发明人： Frederick Ware , Jade Kizer
IPC分类号： H04L7/00 , H04L27/00
CPC分类号： H03M5/16 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K3/356026 , H03K19/01855 , H03M5/20 , H04L25/0272 , H04L25/4906 , H04L25/4917
摘要： Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
摘要翻译：公开了一种具有嵌入式时钟的多线编码技术。在一个特定的示例性实施例中，这些技术可以被实现为发射器部件。发射机组件可以包括至少一个编码器模块以产生一组符号，每个符号由一组线路上的信号电平的组合来表示。发射机组件还可以包括至少一个信令模块，用于根据传输时钟在一组线路上传输一个或多个符号。发射机组件可以另外包括控制逻辑，以将该组符号的第一和第二子集的发射限制到发射时钟的时钟周期的相应的第一和第二部分，使得在该组线路中的至少两个之间的信号差分表现出与发送时钟频率相同的开关行为。

3. 发明授权

US07592824B2 Method and apparatus for test and characterization of semiconductor components 有权
标题翻译：用于半导体元件测试和表征的方法和装置
公开(公告)号：US07592824B2
公开(公告)日：2009-09-22
申请号：US10768443
申请日：2004-01-30
申请人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
发明人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

4. 发明申请

US20090059642A1 Memory Controller With Multi-Modal Reference Pad 有权
标题翻译：具有多模态参考电压的存储控制器
公开(公告)号：US20090059642A1
公开(公告)日：2009-03-05
申请号：US12204728
申请日：2008-09-04
申请人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
发明人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
IPC分类号： G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C5/063 , G11C5/147
摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.
摘要翻译：存储器控制器以两种模式操作以支持不同类型的存储器件。在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。参考电压使用可替换地用于例如电极的焊盘传送。定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

5. 发明申请

US20080091907A1 Integrated circuit memory device having delayed write timing based on read response time 有权
标题翻译：具有基于读取响应时间的延迟写入定时的集成电路存储器件
公开(公告)号：US20080091907A1
公开(公告)日：2008-04-17
申请号：US11953803
申请日：2007-12-10
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarre , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarre , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

6. 发明申请

US20070300038A1 Memory Controller for Non-Homogeneous Memory System 有权
标题翻译：非均匀内存系统的内存控制器
公开(公告)号：US20070300038A1
公开(公告)日：2007-12-27
申请号：US11852996
申请日：2007-09-10
申请人： Frederick Ware
发明人： Frederick Ware
IPC分类号： G06F12/06
CPC分类号： G06F12/10 , G06F12/0292 , G06F12/08 , G06F12/0804 , G06F2212/2022 , G06F2212/205 , Y02D10/13
摘要： A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.
摘要翻译：存储器控制器包括适于耦合到具有第一组属性的第一存储器类型的一个或多个第一存储器件的至少一个接口以及具有第二组属性的第二存储器类型的一个或多个第二存储器件。第一和第二组属性具有至少一个不同的属性。控制器还包括接口逻辑，其被配置为将具有预定义的第一特性的存储器事务定向到第一存储器设备，并且将具有预定义的第二特性的存储器事务定向到第二存储器设备。具有大量写入操作的使用特性的页面可以被映射到一个或多个第一存储器设备，而具有只读或读取主要使用特性的页面可以映射到一个或多个第二存储器设备。

7. 发明申请

US20070280393A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
标题翻译：通信通道校准条件
公开(公告)号：US20070280393A1
公开(公告)日：2007-12-06
申请号：US11754102
申请日：2007-05-25
申请人： Frederick Ware , Richard Perego , Craig Hampel
发明人： Frederick Ware , Richard Perego , Craig Hampel
IPC分类号： H04L7/00
CPC分类号： H04L1/242 , G11C7/04 , G11C7/1057 , G11C7/1084 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/2254 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12 , H04L27/00
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译：方法和系统提供在通信信道的正常操作期间不时地执行校准周期。校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。使用第二组件上的接收器从通信链路接收校准模式。响应于所接收的校准模式来确定通信信道的参数的校准值。校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

8. 发明申请

US20070247935A1 Clocked Memory System with Termination Component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US20070247935A1
公开(公告)日：2007-10-25
申请号：US11767983
申请日：2007-06-25
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

9. 发明申请

US20070147143A1 Integrated Circuit Memory Device Having Delayed Write Capability 失效
标题翻译：具有延迟写入能力的集成电路存储器件
公开(公告)号：US20070147143A1
公开(公告)日：2007-06-28
申请号：US11681375
申请日：2007-03-02
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.
摘要翻译：集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

10. 发明申请

US20060291574A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
公开(公告)号：US20060291574A1
公开(公告)日：2006-12-28
申请号：US11459294
申请日：2006-07-21
申请人： Frederick Ware , Richard Perego , Craig Hampel
发明人： Frederick Ware , Richard Perego , Craig Hampel
IPC分类号： H04L25/00
CPC分类号： H04L1/242 , G11C7/04 , G11C7/1057 , G11C7/1084 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/2254 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12 , H04L27/00
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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