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1. 发明申请

US20110104997A1 APPARATUSES AND METHODS FOR POLISHING AND CLEANING SEMICONDUCTOR WAFERS 审中-公开
标题翻译：抛光和清洁半导体波形的设备和方法
公开(公告)号：US20110104997A1
公开(公告)日：2011-05-05
申请号：US12912738
申请日：2010-10-26
申请人： In-Kwon Jeong
发明人： In-Kwon Jeong
IPC分类号： B24B27/00
CPC分类号： B24B37/10 , B24B37/345 , H01L21/67219
摘要： Wafer processing apparatuses and methods for polishing and cleaning semiconductor wafers with high productivity, small footprint, easy maintenance and low defectivity are provided. The apparatuses comprise a polishing apparatus and a cleaning apparatus. The polishing apparatus comprises at least one polishing module. Each module comprises at least one polishing surface, at least one polishing head, at least one wafer transfer station and a transport mechanism to transfer the at least one polishing head between the at least one polishing surface and the at least one wafer transfer station. The polishing module may comprise a shield member and fluid injection devices to protect the at least one polishing surface from foreign particles. The cleaning apparatus can comprise two or more dry chambers for high productivity. The wafer processing apparatuses can comprise two cleaning apparatuses for high productivity.
摘要翻译：提供了具有高生产率，小占地面积，易维护和低缺陷性的抛光和清洁半导体晶片的晶片加工设备和方法。该装置包括抛光装置和清洁装置。抛光装置包括至少一个抛光模块。每个模块包括至少一个抛光表面，至少一个抛光头，至少一个晶片传送站和传送机构，用于在至少一个抛光表面和至少一个晶片传送站之间传送至少一个抛光头。抛光模块可以包括屏蔽构件和流体注入装置，以保护至少一个抛光表面免受异物的影响。清洁装置可以包括两个或更多个干室，用于高生产率。晶片处理装置可以包括两个用于高生产率的清洁装置。

2. 发明授权

US07928465B2 Method of fabricating vertical structure LEDs 有权
标题翻译：制造垂直结构LED的方法
公开(公告)号：US07928465B2
公开(公告)日：2011-04-19
申请号：US12797335
申请日：2010-06-09
申请人： Jong-Lam Lee , In-Kwon Jeong , Myung Cheol Yoo
发明人： Jong-Lam Lee , In-Kwon Jeong , Myung Cheol Yoo
IPC分类号： H01L33/00
CPC分类号： H01L33/12 , H01C7/006 , H01C7/008 , H01L27/0802 , H01L28/20 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L33/0095 , H01L33/06 , H01L33/32 , H01L33/36 , H01L33/38 , H01L33/40 , H01L33/44 , H01L33/62 , Y10S438/958 , Y10S438/977
摘要： A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
摘要翻译：在诸如蓝宝石的绝缘基板上制造诸如GaN LED的半导体器件的方法。使用正常的半导体处理技术在绝缘基板上制造半导体层。然后，通过使用电感耦合的等离子体反应离子蚀刻，有利地通过半导体层形成限定各个器件的边界的沟槽并进入绝缘衬底。然后用容易去除的层填充沟槽。然后在半导体层（例如通过电镀或通过沉积）形成金属支撑结构，并且去除绝缘基板。然后将电触点，钝化层和金属焊盘添加到各个器件中，然后将各个器件切出。

3. 发明授权

US07674154B2 Apparatus and method for polishing objects using object cleaners 失效
标题翻译：使用对象清洁剂抛光物体的设备和方法
公开(公告)号：US07674154B2
公开(公告)日：2010-03-09
申请号：US11517903
申请日：2006-09-08
申请人： In Kwon Jeong
发明人： In Kwon Jeong
IPC分类号： B24B49/00
CPC分类号： B24B37/345 , B08B7/04 , B08B13/00 , B24B37/04 , H01L21/67219 , H01L21/67742
摘要： An apparatus and method for polishing objects, such as semiconductor wafers, uses at least one object cleaner, which may be a movable object cleaner. The movable object cleaner allows access to different parts of the apparatus for maintenance.
摘要翻译：用于抛光诸如半导体晶片的物体的设备和方法使用至少一个物体清洁器，其可以是可移动物体清洁器。可移动物体清洁器允许进入装置的不同部分进行维护。

4. 发明授权

US07563629B2 Method of fabricating vertical structure LEDs 有权
公开(公告)号：US07563629B2
公开(公告)日：2009-07-21
申请号：US11232957
申请日：2005-09-23
申请人： Jong-Lam Lee , In-Kwon Jeong , Myung Cheol Yoo
发明人： Jong-Lam Lee , In-Kwon Jeong , Myung Cheol Yoo
IPC分类号： H01L51/56 , H01L27/15
CPC分类号： H01L33/12 , H01C7/006 , H01C7/008 , H01L27/0802 , H01L28/20 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L33/0095 , H01L33/06 , H01L33/32 , H01L33/36 , H01L33/38 , H01L33/40 , H01L33/44 , H01L33/62 , Y10S438/958 , Y10S438/977
摘要： A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

5. 发明授权

US07238614B2 Methods for fabricating one or more metal damascene structures in a semiconductor wafer 失效
标题翻译：在半导体晶片中制造一个或多个金属镶嵌结构的方法
公开(公告)号：US07238614B2
公开(公告)日：2007-07-03
申请号：US11270270
申请日：2005-11-08
申请人： In Kwon Jeong
发明人： In Kwon Jeong
IPC分类号： H01L23/495
CPC分类号： H01L21/7684 , H01L21/31053 , H01L21/32115 , H01L21/3212 , H01L21/32125
摘要： Methods for fabricating one or more metal (e.g., copper) damascene structures in a semiconductor wafer use at least three polishing steps to reduce erosion topography in the resulting metal damascene structures and/or increase throughput. The polishing steps may be performed at four polishing units of a polishing apparatus, which may include one or more pivotable load/unload cups to transfer the semiconductor wafer between some of the polishing units.
摘要翻译：在半导体晶片中制造一个或多个金属（例如铜）镶嵌结构的方法使用至少三个抛光步骤以减少所得金属镶嵌结构中的侵蚀形貌和/或增加生产量。抛光步骤可以在抛光装置的四个抛光单元处执行，抛光装置可以包括一个或多个可枢转的装载/卸载杯，以在一些抛光单元之间传送半导体晶片。

6. 发明申请

US20060281393A1 Chemical mechanical polishing tool, apparatus and method 审中-公开
公开(公告)号：US20060281393A1
公开(公告)日：2006-12-14
申请号：US11149287
申请日：2005-06-10
申请人： In Kwon Jeong
发明人： In Kwon Jeong
IPC分类号： B24B1/00 , B24B7/30
CPC分类号： B24B37/11 , B24B37/30
摘要： A chemical mechanical polishing tool, apparatus and method. The polishing tool includes a central polishing assembly comprised of a central pad mount on a central shaft. That central pad mount beneficially retains a center polishing pad. Also included is a ring polishing assembly comprised of a ring pad mount with a central aperture on a ring shaft with a central aperture. The ring pad mount beneficially retains a ring polishing pad having a central aperture. The central polishing assembly and the ring polishing assembly beneficially rotate and move axially independently of one another. The apparatus includes the CMP polishing tool and a rotating polishing table. The method includes rotating a semiconductor wafer on the rotating polishing table. Then, selectively and independently moving a solid center polishing pad having an axis of rotation and/or an axially aligned ring-shaped polishing pad into contact with the surface of the semiconductor wafer.

7. 发明申请

US20050282472A1 CMP apparatus and method for polishing multiple semiconductor wafers on a single polishing pad using multiple slurry delivery lines 审中-公开
公开(公告)号：US20050282472A1
公开(公告)日：2005-12-22
申请号：US11209666
申请日：2005-08-24
申请人： In Kwon Jeong
发明人： In Kwon Jeong
IPC分类号： B24B37/04 , B24B57/02 , H01L21/312 , H01L21/768 , H01L23/522 , H01L23/532 , B24B1/00
CPC分类号： H01L21/76835 , B24B37/04 , B24B57/02 , H01L21/3212 , H01L21/76802 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A chemical mechanical polishing (CMP) apparatus and method for sequentially polishing multiple semiconductor wafers on a single polishing pad utilizes multiple slurry delivery lines to supply one or more types of polishing solutions to the surface of the polishing pad. The slurry delivery lines are positioned to direct the polishing solution or solutions to different polishing positions of the polishing pad. The use of multiple slurry delivery lines allows the CMP apparatus to polish the semiconductor wafers at different polishing positions of the polishing pad using different types of polishing solutions.

8. 发明申请

US20050098792A1 Method of fabricating vertical structure LEDs 有权
标题翻译：制造垂直结构LED的方法
公开(公告)号：US20050098792A1
公开(公告)日：2005-05-12
申请号：US11002413
申请日：2004-12-03
申请人： Jong-Lam Lee , In-Kwon Jeong , Myung Yoo
发明人： Jong-Lam Lee , In-Kwon Jeong , Myung Yoo
IPC分类号： H01C7/00 , H01L21/02 , H01L27/08 , H01L33/00 , H01L33/32 , H01L33/44 , H01L21/00
CPC分类号： H01L33/12 , H01C7/006 , H01C7/008 , H01L27/0802 , H01L28/20 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L33/0095 , H01L33/06 , H01L33/32 , H01L33/36 , H01L33/38 , H01L33/40 , H01L33/44 , H01L33/62 , Y10S438/958 , Y10S438/977
摘要： A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
摘要翻译：在诸如蓝宝石的绝缘基板上制造诸如GaN LED的半导体器件的方法。使用正常的半导体处理技术在绝缘基板上制造半导体层。然后，通过使用电感耦合的等离子体反应离子蚀刻，有利地通过半导体层形成限定各个器件的边界的沟槽并进入绝缘衬底。然后用容易去除的层填充沟槽。然后在半导体层（例如通过电镀或通过沉积）形成金属支撑结构，并且去除绝缘基板。然后将电触点，钝化层和金属焊盘添加到各个器件中，然后将各个器件切出。

9. 发明授权

US06465351B1 Method of forming a capacitor lower electrode using a CMP stopping layer 失效
标题翻译：使用CMP停止层形成电容器下电极的方法
公开(公告)号：US06465351B1
公开(公告)日：2002-10-15
申请号：US09563716
申请日：2000-05-02
申请人： In-Kwon Jeong
发明人： In-Kwon Jeong
IPC分类号： H01L21302
CPC分类号： H01L27/10852 , H01L21/31053 , H01L27/10814 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A method for fabricating a capacitor is provided that can reduce the number of CMP processes. It avoids the use of a CMP process on an uneven interlayer insulating layer on which a storage node is to be formed, by employing a process of forming a sacrificial oxide layer on the uneven interlayer insulating layer, forming a CMP stopper layer, forming another oxide layer, etching the deposited layers until a top surface of uneven interlayer insulating layer is exposed to form a trench therein for a storage node, depositing a conductive material in the trench and on the another oxide, and performing a CMP process until a top surface of the CMP stopper layer is exposed to electrically separate each storage node from another. The remainder of the oxide layer on the CMP stopper layer is then removed and then the CMP stopper layer is removed.
摘要翻译：提供一种制造电容器的方法，其可以减少CMP工艺的数量。通过在不均匀的层间绝缘层上形成牺牲氧化层，形成CMP阻挡层，形成另一种氧化物的方法，避免了在要形成存储节点的不均匀层间绝缘层上使用CMP工艺蚀刻沉积的层，直到暴露不均匀层间绝缘层的顶表面以形成用于存储节点的沟槽，在沟槽中和另一氧化物上沉积导电材料，并执行CMP工艺，直到 CMP停止层被暴露以将每个存储节点与另一个存储节点电隔离。然后去除CMP停止层上的氧化物层的剩余部分，然后除去CMP阻挡层。

10. 发明授权

US06251790B1 Method for fabricating contacts in a semiconductor device 有权
标题翻译：在半导体器件中制造触点的方法
公开(公告)号：US06251790B1
公开(公告)日：2001-06-26
申请号：US09351083
申请日：1999-07-09
申请人： In-Kwon Jeong
发明人： In-Kwon Jeong
IPC分类号： H01L2144
CPC分类号： H01L21/76831 , H01L21/76816 , H01L21/76844 , H01L21/76877 , H01L21/76885
摘要： A contact structure between two conductors in a semiconductor device and a method for fabricating the same which can increase alignment margins between the contact plug and overlying conductor are provided. The contact plug includes a lower conductor formed on a semiconductor substrate, an insulating layer formed on the lower conductor and on the semiconductor substrate, the insulating layer having a contact hole, a contact plug recess a predetermined depth from a top surface of the insulating layer in the contact hole, and a sidewall spacer formed on both lateral sidewalls of remainder of the contact hole. The contact plug structure is made by a process of forming a recessed contact plug in the contact hole formed in an insulating layer. Sidewall spacer is formed on both sidewalls of the remainder of the contact hole that has low aspect ratio as compared to that of the contact hole prior to the formation of the recessed contact plug. The resulting sidewall spacer can have good deposition profile and serves to reduce critical dimension of the contact hole.
摘要翻译：提供半导体器件中的两个导体之间的接触结构及其制造方法，其可以增加接触插塞和上覆导体之间的对准边缘。接触插塞包括形成在半导体衬底上的下导体，形成在下导体上和在半导体衬底上的绝缘层，绝缘层具有接触孔，从绝缘层顶表面预定深度的接触塞凹槽在接触孔中，以及形成在接触孔的剩余部分的两个侧壁上的侧壁间隔物。接触插塞结构通过在形成在绝缘层中的接触孔中形成凹入的接触插塞的过程来制成。侧壁间隔件形成在接触孔的其余部分的两个侧壁上，与形成凹形接触塞之前的接触孔相比，其纵横比低。所产生的侧壁间隔物可以具有良好的沉积轮廓并用于减小接触孔的临界尺寸。

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