专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06699749B1 Method for manufacturing a metal-insulator-metal capacitor 失效
标题翻译：金属 - 绝缘体 - 金属电容器的制造方法
公开(公告)号：US06699749B1
公开(公告)日：2004-03-02
申请号：US10429321
申请日：2003-05-05
申请人： Seung-Gun Lee , Il-Goo Kim , Ho-Sen Chang , Ju-Hyuk Chang , Sang-Rok Hah
发明人： Seung-Gun Lee , Il-Goo Kim , Ho-Sen Chang , Ju-Hyuk Chang , Sang-Rok Hah
IPC分类号： H01L218242
CPC分类号： H01L21/02071 , H01L21/32136 , H01L28/60
摘要： A method of manufacturing a MIM capacitor having a bottom electrode is provided by forming a metal wire including copper on a substrate. After the metal wire is formed on the substrate, a dielectric film is formed on the metal wire. A top electrode film is formed on the dielectric film, and then the top electrode film is etched to form a top electrode. A hard metallic polymer formed during the etching of the top electrode film is removed using a mixture of an oxygen gas and a fluorocarbon based gas. The lifting of the thin films is effectively prevented, and the yield of the manufacturing process for manufacturing a MIM capacitor is increased. Additionally, the MIM capacitor has a uniform capacitance because the damage to the dielectric film is prevented, and the oxidation of the bottom electrode is also prevented.
摘要翻译：通过在基板上形成包含铜的金属线来提供制造具有底部电极的MIM电容器的方法。在基板上形成金属线之后，在金属线上形成电介质膜。在电介质膜上形成顶部电极膜，然后蚀刻顶部电极膜以形成顶部电极。使用氧气和碳氟化合物气体的混合物除去在顶部电极膜的蚀刻期间形成的硬质金属聚合物。有效地防止薄膜的提升，并且制造MIM电容器的制造工艺的成品率提高。此外，MIM电容器具有均匀的电容，因为防止对电介质膜的损坏，并且还防止了底部电极的氧化。

2. 发明授权

US07157366B2 Method of forming metal interconnection layer of semiconductor device 有权
标题翻译：形成半导体器件金属互连层的方法
公开(公告)号：US07157366B2
公开(公告)日：2007-01-02
申请号：US10888577
申请日：2004-07-09
申请人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
发明人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.
摘要翻译：提供用于形成半导体器件的金属互连层的各种方法。用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔，沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔并且用导电材料填充整个通孔和沟槽互连区域。

3. 发明授权

US07026242B2 Method for filling a hole with a metal 有权
标题翻译：用金属填充孔的方法
公开(公告)号：US07026242B2
公开(公告)日：2006-04-11
申请号：US10802411
申请日：2004-03-16
申请人： Hong-Seong Son , Sang-Rok Hah , Il-Goo Kim , Jun-Hwan Oh
发明人： Hong-Seong Son , Sang-Rok Hah , Il-Goo Kim , Jun-Hwan Oh
IPC分类号： H01L21/4763
CPC分类号： H01L21/2885 , H01L21/76877
摘要： In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.
摘要翻译：在用金属填充孔的方法中，在半导体衬底上依次形成绝缘层，第一掩模层和第二掩模层。使用光致抗蚀剂图案蚀刻第一和第二掩模层以形成第一和第二掩模。使用蚀刻剂选择性地蚀刻第一掩模层图案，第一掩模层图案相对于蚀刻剂具有比第二层图案更高的蚀刻选择性，以形成具有加宽开口的第三掩模层图案。使用第二掩模蚀刻绝缘层，以在绝缘层中形成孔。在孔和第三开口中形成金属层。金属层被平坦化以形成埋在孔中的金属塞，而没有凹陷或空隙。

4. 发明授权

US06924228B2 Method of forming a via contact structure using a dual damascene technique 有权
标题翻译：使用双镶嵌技术形成通孔接触结构的方法
公开(公告)号：US06924228B2
公开(公告)日：2005-08-02
申请号：US10748900
申请日：2003-12-30
申请人： Il-Goo Kim , Sang-Rok Hah
发明人： Il-Goo Kim , Sang-Rok Hah
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76829
摘要： A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern. The inter-metal dielectric layer is partially etched using the hard mask pattern as an etching mask, thereby forming a trench in the inter-metal dielectric layer. The second sacrificial layer pattern is selectively removed to expose the the lower interconnection line.
摘要翻译：提供了一种使用双镶嵌技术形成通孔接触结构的方法。该方法包括在半导体衬底上形成下互连线，并且在具有下互连线的半导体衬底上依次形成金属间介电层和硬掩模层。硬掩模层和金属间介电层被成功地图案化以形成暴露下部连接线的通孔。在硬掩模层上形成填充通孔的牺牲层。牺牲层和硬掩模层被图案化以形成具有穿过通孔的开口的第一牺牲层图案和保留在通孔中的第二牺牲层图案，并且同时在第一牺牲层下方形成硬掩模图案层图案。使用硬掩模图案作为蚀刻掩模来部分地蚀刻金属间介电层，从而在金属间介电层中形成沟槽。选择性地去除第二牺牲层图案以暴露下部互连线。

5. 发明授权

US07033944B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US07033944B2
公开(公告)日：2006-04-25
申请号：US10654770
申请日：2003-09-04
申请人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
发明人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76808
摘要： A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.
摘要翻译：公开了一种双镶嵌工艺。根据本发明的双镶嵌工艺，通过金属间电介质层的第一凹陷区域填充有底部保护层，同时蚀刻底部保护层和金属间电介质层，以形成第二凹陷区域，该凹陷区域具有通过使用蚀刻气体相对于底部保护层选择性地蚀刻金属间电介质层，比第一凹陷区域上的第一凹陷区域更浅的深度和更宽的宽度。换句话说，相对于底部保护层的蚀刻选择比，金属间电介质层优选为约0.5至约1.5。因此，可以形成双重镶嵌结构而不形成副产物或氧化物栅栏。

6. 发明申请

US20050037605A1 Method of forming metal interconnection layer of semiconductor device 有权
标题翻译：形成半导体器件金属互连层的方法
公开(公告)号：US20050037605A1
公开(公告)日：2005-02-17
申请号：US10888577
申请日：2004-07-09
申请人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
发明人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.
摘要翻译：提供用于形成半导体器件的金属互连层的各种方法。用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔，沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔并且用导电材料填充整个通孔和沟槽互连区域。

7. 发明申请

US20050048875A1 Chemical mechanical polishing apparatus 失效
公开(公告)号：US20050048875A1
公开(公告)日：2005-03-03
申请号：US10850688
申请日：2004-05-21
申请人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
发明人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
IPC分类号： B24B37/02 , B24B37/04 , B24B49/10 , B24B49/14 , B24B49/00 , B24B1/00
CPC分类号： B24B37/013 , B24B49/10 , B24B49/14
摘要： There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

8. 发明申请

US20080166851A1 METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：金属绝缘子金属（MIM）电容器及其制造方法
公开(公告)号：US20080166851A1
公开(公告)日：2008-07-10
申请号：US12030476
申请日：2008-02-13
申请人： Uk-Sun HONG , Sang-Rok Hah , Hong-Seong Son
发明人： Uk-Sun HONG , Sang-Rok Hah , Hong-Seong Son
IPC分类号： H01L21/02
CPC分类号： H01G4/33 , H01L21/31144 , H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.
摘要翻译：本发明公开了一种金属绝缘体金属（MIM）电容器及其制造方法，包括在具有金属线的半导体基板上形成底部绝缘层，电容器电极材料层和硬掩模材料层上; 通过使用感光掩模蚀刻硬掩模材料层来形成硬掩模; 通过使用硬掩模作为蚀刻掩模来蚀刻电容器电极材料层来形成电容器电极; 以及在半导体的整个表面上形成顶部绝缘层。

9. 发明授权

US07183226B2 Method of forming a trench for use in manufacturing a semiconductor device 有权
标题翻译：形成用于制造半导体器件的沟槽的方法
公开(公告)号：US07183226B2
公开(公告)日：2007-02-27
申请号：US10673873
申请日：2003-09-30
申请人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
发明人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/10885 , H01L21/76229 , H01L21/76232 , H01L29/66181
摘要： A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成光致抗蚀剂图案，执行第一蚀刻工艺，其中使用光致抗蚀剂图案作为掩模形成初始沟槽，并且执行第二不同的蚀刻工艺以扩大初始沟槽。因此，可以使用具有稳定结构的光致抗蚀剂图案来形成初始沟槽。此后，使用具有基于其中形成初始沟槽的材料的组成的蚀刻溶液（例如硅衬底或绝缘膜）来扩大沟槽。因此，可以在扩大的沟槽中形成金属布线，隔离膜或接触件到期望的尺寸。

10. 发明授权

US06976902B2 Chemical mechanical polishing apparatus 失效
标题翻译：化学机械抛光装置
公开(公告)号：US06976902B2
公开(公告)日：2005-12-20
申请号：US10850688
申请日：2004-05-21
申请人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
发明人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
IPC分类号： B24B37/02 , B24B37/04 , B24B49/10 , B24B49/14 , B24B1/00
CPC分类号： B24B37/013 , B24B49/10 , B24B49/14
摘要： There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.
摘要翻译：提供了一种化学机械抛光装置，其可以包括由抛光台马达旋转并且具有垫的抛光台，位于抛光台上方的载体头可以通过载体头马达的驱动旋转并具有晶片位于其底部的浆料供应器，用于向抛光台的上部供应浆料;第一抛光终点检测器，用于通过温度传感器的温度变化检测抛光终点;至少一个检测温度传感器抛光区域（晶片，焊盘和浆料）的温度，以及用于从承载头电动机的负载电流，电压和电阻的变化检测抛光终点的第二抛光终点检测器。此外，代替第二研磨终点检测器，可以采用光信号抛光终点检测器，用于通过照射在晶片上的光并从晶片反射来检测抛光终点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式