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1. 发明申请

US20090052252A1 METHODS OF APPLYING READ VOLTAGES IN NAND FLASH MEMORY ARRAYS 审中-公开
标题翻译：在NAND闪存阵列中应用读取电压的方法
公开(公告)号：US20090052252A1
公开(公告)日：2009-02-26
申请号：US12254205
申请日：2008-10-20
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.
摘要翻译：提供了一种提高闪存阵列的读取干扰特性的方法。根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。将接地电压施加到从存储单元中选择的存储单元的字线。第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。然后，将第一读取电压施加到未被选择的其他存储单元。第二读取电压低于第一读取电压。

2. 发明申请

US20080101122A1 Methods of applying read voltages in NAND flash memory arrays 有权
标题翻译：在NAND闪存阵列中应用读取电压的方法
公开(公告)号：US20080101122A1
公开(公告)日：2008-05-01
申请号：US11635995
申请日：2006-12-08
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.
摘要翻译：提供了一种提高闪存阵列的读取干扰特性的方法。根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。将接地电压施加到从存储单元中选择的存储单元的字线。第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。然后，将第一读取电压施加到未被选择的其他存储单元。第二读取电压低于第一读取电压。

3. 发明授权

US07457160B2 Methods of applying read voltages in NAND flash memory arrays 有权
公开(公告)号：US07457160B2
公开(公告)日：2008-11-25
申请号：US11635995
申请日：2006-12-08
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

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