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1. 发明申请

US20120052648A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120052648A1
公开(公告)日：2012-03-01
申请号：US13221099
申请日：2011-08-30
申请人： Hyung-Shin Kwon , Hyung-Dong Kim
发明人： Hyung-Shin Kwon , Hyung-Dong Kim
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L27/10814 , H01L27/10894 , H01L27/10897 , H01L28/90
摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.
摘要翻译：半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。提供了与具有相对较大高度的下电极接触的支撑层图案。支撑层图案设置在用于支撑下电极的下电极之间。电介质层设置在下电极和支撑层图案上。在电介质层上形成上电极，具有平坦的上表面。在上电极上设置金属间介电层。形成穿过金属间介电层并与上电极接触的金属接触。金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。该设备具有较高的可靠性。

2. 发明授权

US08051341B2 Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit 失效
标题翻译：具有测试地址产生电路的半导体存储器件和具有测试地址产生电路的半导体存储器件的测试方法
公开(公告)号：US08051341B2
公开(公告)日：2011-11-01
申请号：US12214453
申请日：2008-06-19
申请人： Yong-Hwan Cho , Hyung-Dong Kim , Woo-II Kim
发明人： Yong-Hwan Cho , Hyung-Dong Kim , Woo-II Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.
摘要翻译：半导体存储器件包括在该器件上配置的测试地址产生电路。测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

3. 发明申请

US20100302883A1 Method of estimating self refresh period of semiconductor memory device 有权
标题翻译：估计半导体存储器件的自刷新周期的方法
公开(公告)号：US20100302883A1
公开(公告)日：2010-12-02
申请号：US12798196
申请日：2010-03-31
申请人： Hyung-Dong Kim , Byung-Hwan So
发明人： Hyung-Dong Kim , Byung-Hwan So
IPC分类号： G11C7/00 , G11C8/04
CPC分类号： G11C11/406 , G11C8/04 , G11C11/40615 , G11C2211/4061 , G11C2211/4067
摘要： In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.
摘要翻译：在根据示例性实施例的估计半导体存储器件的自刷新周期的方法中，响应于刷新复位信号复位多个内部地址信号。多个内部地址信号与振荡信号同步地顺序地改变。基于多个内部地址信号产生刷新完成信号。基于刷新复位信号和刷新完成信号来检测自刷新周期。

4. 发明申请

US20080158875A1 LIGHT MODULE AND FLAT LIGHT UNIT IN A LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置中的光模块和平板光单元
公开(公告)号：US20080158875A1
公开(公告)日：2008-07-03
申请号：US11955029
申请日：2007-12-12
申请人： Jae Bum Kim , Jae Kyung Kang , Sung Keun Lee , Jae Jin Kim , Hyung Dong Kim , Sang Dae Lee
发明人： Jae Bum Kim , Jae Kyung Kang , Sung Keun Lee , Jae Jin Kim , Hyung Dong Kim , Sang Dae Lee
IPC分类号： F21V5/00
CPC分类号： G02B19/0066 , G02B19/0014 , G02B27/0955 , G02F1/133603
摘要： A liquid crystal display device may include a backlight unit for providing light for the display. A backlight unit may include light modules. The light modules include colored LEDs surrounded by a first lens for refracting the light from the LEDs. A second lens surrounds the first lens for further refraction of the light to improve brightness and the uniformity of the light.
摘要翻译：液晶显示装置可以包括用于为显示器提供光的背光单元。背光单元可以包括光模块。光模块包括被第一透镜包围的彩色LED，以折射来自LED的光。第二透镜围绕第一透镜以进一步折射光以改善光的亮度和均匀性。

5. 发明授权

US07365571B2 Input buffer with wide input voltage range 失效
公开(公告)号：US07365571B2
公开(公告)日：2008-04-29
申请号：US11037083
申请日：2005-01-19
申请人： Dong-il Seo , Hyung-dong Kim , Jung-sik Kim
发明人： Dong-il Seo , Hyung-dong Kim , Jung-sik Kim
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018528
摘要： The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

6. 发明申请

US20070253219A1 Backlight assembly and liquid crystal display device having the same 有权
标题翻译：背光组件和具有该背光组件的液晶显示装置
公开(公告)号：US20070253219A1
公开(公告)日：2007-11-01
申请号：US11581369
申请日：2006-10-17
申请人： Hyung Dong Kim , Wook Jeon
发明人： Hyung Dong Kim , Wook Jeon
IPC分类号： F21V7/04
CPC分类号： G02F1/133603 , F21V19/0055 , F21Y2103/10 , F21Y2107/50 , F21Y2115/10 , G02F1/133608
摘要： A backlight assembly and a liquid crystal display device having the same backlight assembly are provided. The backlight assembly includes a bottom case, a plurality of printed circuit boards (PCBs) disposed on the bottom case, wherein substantially all of the PCBs have predetermined inclinations with respect to a front surface of the bottom case, and a plurality of light emitting diodes (LEDs) mounted on the PCBs.
摘要翻译：提供具有相同背光组件的背光组件和液晶显示装置。背光组件包括底壳，设置在底壳上的多个印刷电路板（PCB），其中基本上所有的PCB相对于底壳的前表面具有预定的倾斜角，并且多个发光二极管（LED）安装在PCB上。

7. 发明申请

US20060255477A1 Pad structure, pad layout structure, and pad layout method in semiconductor devices 有权
标题翻译：衬垫结构，衬垫布局结构和衬垫布局方法在半导体器件中
公开(公告)号：US20060255477A1
公开(公告)日：2006-11-16
申请号：US11358898
申请日：2006-02-21
申请人： Na-Rae Kim , Tae-Sik Son , Hee-Joong Oh , Byung-Heon Kwak , Jae-Hoon Joo , Hyung-Dong Kim , Young-Min Jang
发明人： Na-Rae Kim , Tae-Sik Son , Hee-Joong Oh , Byung-Heon Kwak , Jae-Hoon Joo , Hyung-Dong Kim , Young-Min Jang
IPC分类号： H01L23/48
CPC分类号： H01L24/03 , H01L22/32 , H01L24/05 , H01L24/06 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05552 , H01L2224/05553 , H01L2224/0603 , H01L2224/45144 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/19041 , H01L2224/48 , H01L2924/00
摘要： In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.
摘要翻译：在衬垫的布局结构和用于半导体器件的测试或引线键合的衬垫的结构中，至少一个或多个非线接合焊盘的尺寸与至少一个或多个用于半导体器件的引线接合的焊盘。在焊盘结构中，焊盘包括导线接合区域，其具有用于在确定的焊盘尺寸内的顶部金属层的一部分的压花表面以改善接合过程，以及不具有压花表面的探针末端接触区域在确定的焊盘尺寸内的顶部金属层的表面部分，以便在装置的测试期间减少探针尖端的磨损。因此，可以在有限的区域内增加衬垫间距，并且可以在将在常规衬垫形成区域中占据的区域中进一步形成外围电路。从而实现了半导体器件的更高集成度和探针尖端在探测中的磨损。

8. 发明授权

US06856563B2 Semiconductor memory device for enhancing bitline precharge time 失效
标题翻译：用于增强位线预充电时间的半导体存储器件
公开(公告)号：US06856563B2
公开(公告)日：2005-02-15
申请号：US10659249
申请日：2003-09-11
申请人： Hyung-Dong Kim , Chi-Sung Oh
发明人： Hyung-Dong Kim , Chi-Sung Oh
IPC分类号： G11C11/4091 , G11C7/12 , G11C8/02 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.
摘要翻译：提供一种用于增强位线预充电时间的半导体存储器件和用于加速器件中的预充电时间的方法，其可以减少总体预充电时间，以努力保证半导体存储器件中的适当的高速操作。在该方法中，均衡使能信号可以被施加到器件的均衡器，以对连接存储器单元，器件的隔离部分和读出放大器的位线对进行预充电。要施加到一个或多个隔离部分的隔离控制信号可以被延迟给定时间，使得施加隔离控制信号的时间是在将均衡使能信号施加到均衡器的时间之后。

9. 发明授权

US06535447B2 Semiconductor memory device and voltage level control method thereof 失效
公开(公告)号：US06535447B2
公开(公告)日：2003-03-18
申请号：US10000178
申请日：2001-11-30
申请人： Hyung-Dong Kim , Kwang-Hyun Kim
发明人： Hyung-Dong Kim , Kwang-Hyun Kim
IPC分类号： G11C700
CPC分类号： G05F3/242
摘要： The present invention discloses a semiconductor memory device and a voltage level control method thereof. The semiconductor memory device comprises multiple sub high voltage generators, multiple control circuits, a high voltage level detecting circuit, and a mode setting circuit. The multiple sub high voltage generators boost the high voltage level. The multiple control circuits control operations of each of the corresponding multiple sub high voltage generators responsive to each of corresponding high voltage detecting signals and to each of corresponding multiple control signals in the test mode. The high voltage level detecting circuit enabled by an active signal, detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting circuit sets the state of the multiple control signals responsive to the signals from the out side in the test mode. Performing the test by regulating the number of the multiple sub high voltage generators can prevent the semiconductor memory device from over kill. In addition, the test of the package state can be performed by enabling a few of the voltage generators than necessary for the full operation of the test mode.

10. 发明授权

US06426902B1 Semiconductor memory device having redundancy circuit capable of improving redundancy efficiency 有权
标题翻译：具有能够提高冗余效率的冗余电路的半导体存储器件
公开(公告)号：US06426902B1
公开(公告)日：2002-07-30
申请号：US09657318
申请日：2000-09-07
申请人： Hi-choon Lee , Seung-hoon Lee , Hyung-dong Kim
发明人： Hi-choon Lee , Seung-hoon Lee , Hyung-dong Kim
IPC分类号： G11C700
CPC分类号： G11C29/787 , G11C29/808
摘要： A redundancy circuit is used to repair a normal column containing a defective normal memory cell. The redundancy circuit comprises a redundancy column containing redundancy memory cells and a plurality of programmable decoders. When any one of the plurality of programmable decoders enters a repair mode, a column pre-decoder for selecting a column containing a normal memory cell is disabled. Each of the programmable decoders can be configured to replace a column containing a defective normal memory cell in a single memory bank or a single memory bank group with a redundancy column. Since a defective column is replaced with a redundancy column in individual banks or bank groups, redundancy efficiency is greatly improved by allowing multiple normal columns containing defective cells to be replaced using a single redundancy column.
摘要翻译：冗余电路用于修复包含有缺陷的正常存储器单元的正常列。冗余电路包括冗余列，其包含冗余存储单元和多个可编程解码器。当多个可编程解码器中的任何一个进入修复模式时，用于选择包含正常存储器单元的列的列预解码器被禁用。每个可编程解码器都可以被配置为用冗余列替换包含单个存储体或单个存储体组中的有缺陷的正常存储单元的列。由于缺陷列被替换为单独存储体或存储体组中的冗余列，所以通过允许使用单个冗余列替换包含有缺陷单元的多个正常列，可大大提高冗余效率。

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