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1. 发明申请

US20090153254A1 PHASE LOCKED LOOP CIRCUIT PERFORMING TWO POINT MODULATION AND GAIN CALIBRATION METHOD THEREOF 失效
标题翻译：执行两点调制的相位锁定环路电路及其增益校准方法
公开(公告)号：US20090153254A1
公开(公告)日：2009-06-18
申请号：US12265395
申请日：2008-11-05
申请人： Hwa Yeal Yu , Dong Jin Keum
发明人： Hwa Yeal Yu , Dong Jin Keum
IPC分类号： H03L7/08
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991 , H03L7/0891 , H03L7/093
摘要： A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.
摘要翻译：用于两点调制的PLL电路包括第一环路滤波器，第二环路滤波器，多个开关装置和校准模块。第一个环路滤波器在增益校准操作期间对电荷泵的输出电压进行滤波。第二个环路滤波器在正常运行期间对电荷泵的输出电压进行滤波。第一环路滤波器具有比第二环路滤波器更宽的带宽，以通过减少锁定时间来执行快速校准。第一环路滤波器的操作，第二环路滤波器的操作和第一环路滤波器的断开由开关装置的切换操作决定。在增益校准操作期间，校准模块基于在第一环路滤波器打开之后累积在第一环路滤波器中的频率误差来调整模拟调制数据的增益。

2. 发明申请

US20140253073A1 BI-DIRECTIONAL VOLTAGE POSITIONING CIRCUIT, VOLTAGE CONVERTER AND POWER SUPPLY DEVICE INCLUDING THE SAME 有权
标题翻译：双向电压定位电路，电压转换器和包括其的电源装置
公开(公告)号：US20140253073A1
公开(公告)日：2014-09-11
申请号：US14187442
申请日：2014-02-24
申请人： Sung-Woo MOON , Myeong-Lyong KO , Yu-Seok KO , Dong-Jin KEUM , Hyun-Wook YOO , Hwa-Yeal YU
发明人： Sung-Woo MOON , Myeong-Lyong KO , Yu-Seok KO , Dong-Jin KEUM , Hyun-Wook YOO , Hwa-Yeal YU
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , G05F1/468 , H02M1/44 , H02M3/158 , H02M3/1588 , H02M2001/0009 , H02M2001/0025 , Y02B70/1466
摘要： A bi-directional voltage positioning circuit includes a voltage to current converter, a current mirror circuit and a switch. The voltage to current converter converts a sensing voltage to a first current, and the sensing voltage is sensed based on a current flowing through an output coil connected between a switching node and an output node. The current mirror circuit mirrors the first current to generate a second current and a third current, the second current is N times greater than the first current, the third current is M times greater than the first current, and N and M are real numbers greater than zero. The switch provides a feedback node with one of the second current and third current in response to a switching control signal, and an output voltage of the output node is divided at the feedback node.
摘要翻译：双向电压定位电路包括电压 - 电流转换器，电流镜电路和开关。电压 - 电流转换器将感测电压转换为第一电流，并且基于流过连接在开关节点和输出节点之间的输出线圈的电流来感测感测电压。电流镜电路反射第一电流以产生第二电流和第三电流，第二电流是第一电流的N倍，第三电流是第一电流的M倍，N和M是实数更大比零。该开关响应于开关控制信号向反馈节点提供第二电流和第三电流之一，并且在反馈节点处分配输出节点的输出电压。

3. 发明授权

US07538703B2 Sigma-delta modulation with minimized noise and fractional-N phase-locked loop including the same 失效
$Sigma-delta modulation with minimized noise and fractional-N phase-locked loop including the same$
标题翻译：具有最小化噪声的Σ-Δ调制和包括相同的分数N锁相环
公开(公告)号：US07538703B2
公开(公告)日：2009-05-26
申请号：US11703260
申请日：2007-02-07
申请人： Hwa-Yeal Yu
发明人： Hwa-Yeal Yu
IPC分类号： H03M1/20
CPC分类号： H03L7/1976 , H03M7/3006 , H03M7/3028 , H03M7/304
摘要： A sigma-delta modulator (SDM) includes a delay circuit and an operation circuit. The delay circuit generates multiple clock signals with different delays. The operation circuit includes a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation. Thus, noise may be dispersed for minimizing noise coupling. The SDM is used to particular advantage within a fractional-N phase-locked loop.
摘要翻译： Σ-Δ调制器（SDM）包括延迟电路和运算电路。延迟电路产生具有不同延迟的多个时钟信号。操作电路包括多个操作级，它们根据用于高阶Σ-Δ调制的所有时钟信号的定时进行操作。因此，可以分散噪声以最小化噪声耦合。在分数N锁相环中，SDM被用于特别的优点。

4. 发明申请

US20080048788A1 FREQUENCY TUNING METHOD FOR VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP USING THE SAME 审中-公开
标题翻译：用于电压控制振荡器和相位锁定环路的频率调谐方法
公开(公告)号：US20080048788A1
公开(公告)日：2008-02-28
申请号：US11610012
申请日：2006-12-13
申请人： Hwa-Yeal Yu
发明人： Hwa-Yeal Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/087 , H03L7/099
摘要： A frequency tuning method for a voltage controlled oscillator includes outputting a first frequency selected from 2n discrete frequencies included in a frequency tuning range of the voltage controlled oscillator based on a predetermined control voltage and an n-bit control code during coarse tuning; outputting a third frequency corresponding to an average of the first frequency and a second frequency, that is, ½ of a code interval in response to the predetermined control voltage, the n-bit control code, and a control bit; and locking an output frequency of the voltage controlled oscillator to a reference frequency based on an analog control voltage and the third frequency during fine tuning. The second frequency is adjacent to the first frequency amoung the 2n discrete frequencies and the third frequency is used as an initial frequency in the fine tuning.
摘要翻译：用于压控振荡器的频率调谐方法包括：基于预定的控制电压和n位控制，输出从压控振荡器的频率调谐范围中包含的2个N + 1个离散频率中选出的第一频率粗调时代码; 输出对应于第一频率和第二频率的平均值的第三频率，即响应于预定控制电压的码间隔的1/2，n比特控制码和控制比特; 并且在微调期间基于模拟控制电压和第三频率将压控振荡器的输出频率锁定到参考频率。第二频率与两个离散频率的第一频率相邻，第三频率用作微调中的初始频率。

5. 发明申请

US20070024381A1 Charge supply apparatus and method in frequency synthesizer 失效
标题翻译：频率合成器中的充电电源装置和方法
公开(公告)号：US20070024381A1
公开(公告)日：2007-02-01
申请号：US11496652
申请日：2006-07-31
申请人： Hwa-Yeal Yu
发明人： Hwa-Yeal Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03L7/10 , H03L7/113 , H03L7/18
摘要： A charge supplying apparatus in a frequency synthesizer includes first and second charge supply units. The first charge supply unit is activated for generating a first voltage coupled to a loop filter, and the second charge supply unit is activated for generating a second voltage coupled to the loop filter. A control unit has a mode determining unit that activates one of the first and second charge supply units from comparing a reference frequency with an output frequency. The mode determining unit also generates at least one control signal for adjusting the first voltage by binary increments for decreasing a difference between the reference and output frequencies.
摘要翻译：频率合成器中的电荷供给装置包括第一和第二电荷供给单元。第一电荷供应单元被激活以产生耦合到环路滤波器的第一电压，并且第二电荷供应单元被激活以产生耦合到环路滤波器的第二电压。控制单元具有模式确定单元，其通过将参考频率与输出频率进行比较来激活第一和第二充电电源单元中的一个。模式确定单元还产生用于通过二进制增量来调整第一电压的至少一个控制信号，以减小参考和输出频率之间的差。

6. 发明授权

US10205388B2 Power management integrated circuit for supplying load current information and electronic device having the same 有权
公开(公告)号：US10205388B2
公开(公告)日：2019-02-12
申请号：US14872285
申请日：2015-10-01
申请人： Minho Choi , Yus Ko , Dongjin Keum , Hwa Yeal Yu , Younghoon Lee
发明人： Minho Choi , Yus Ko , Dongjin Keum , Hwa Yeal Yu , Younghoon Lee
IPC分类号： G05F1/10 , G05F3/02 , H02M3/158 , G01R19/00 , H02M1/00
摘要： An electronic device includes a power management integrated circuit (PMIC) including a plurality of regulators. Each of the plurality of regulators has a current meter configured to measure a respective load current. A load device is configured to receive real-time load current information from the PMIC and to perform a performance improvement operation based on the real-time load current information.

7. 发明授权

US07755439B2 Phase locked loop circuit performing two point modulation and gain calibration method thereof 失效
标题翻译：执行两点调制和增益校准方法的锁相环电路
公开(公告)号：US07755439B2
公开(公告)日：2010-07-13
申请号：US12265395
申请日：2008-11-05
申请人： Hwa Yeal Yu , Dong Jin Keum
发明人： Hwa Yeal Yu , Dong Jin Keum
IPC分类号： H03C3/06 , H03L7/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/18
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991 , H03L7/0891 , H03L7/093
摘要： A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.
摘要翻译：用于两点调制的PLL电路包括第一环路滤波器，第二环路滤波器，多个开关装置和校准模块。第一个环路滤波器在增益校准操作期间对电荷泵的输出电压进行滤波。第二个环路滤波器在正常运行期间对电荷泵的输出电压进行滤波。第一环路滤波器具有比第二环路滤波器更宽的带宽，以通过减少锁定时间来执行快速校准。第一环路滤波器的操作，第二环路滤波器的操作和第一环路滤波器的断开由开关装置的切换操作决定。在增益校准操作期间，校准模块基于在第一环路滤波器打开之后累积在第一环路滤波器中的频率误差来调整模拟调制数据的增益。

8. 发明授权

US07424280B2 Frequency synthesizer and frequency synthesis method 有权
标题翻译：频率合成器和频率合成方法
公开(公告)号：US07424280B2
公开(公告)日：2008-09-09
申请号：US11206014
申请日：2005-08-17
申请人： Hwa-Yeal Yu
发明人： Hwa-Yeal Yu
IPC分类号： H04B7/00
CPC分类号： H03L7/1976 , H03L7/23
摘要： A dual frequency synthesizer includes a reference oscillator, an R counter, a first fractional-N phase-locked loop (for a receiving channel) and a second fractional-N phase-locked loop (for a transmitting channel) and one shared sigma-delta modulator. The reference oscillator outputs a reference oscillation frequency clock. The R counter outputs a reference frequency clock based on the reference oscillation frequency clock. The first fractional-N phase-locked loop (PLL) (for a receiving channel) generates a first (receiving channel frequency) clock based on the reference frequency clock. The second fractional-N phase-locked loop (for a transmitting channel) generates a second (transmitting channel frequency) clock based on the same reference frequency clock. Both fractional-N phase-locked loops share a common sigma-delta modulator. Therefore, the chip size of the dual frequency synthesizer may be reduced.
摘要翻译：双频合成器包括参考振荡器，R计数器，第一小数N锁相环（用于接收信道）和第二小数N锁相环（用于发射信道）和一个共享Σ-Δ 调制器。参考振荡器输出参考振荡频率时钟。 R计数器基于参考振荡频率时钟输出参考频率时钟。第一分数N锁相环（PLL）（用于接收信道）基于参考频率时钟产生第一（接收信道频率）时钟。第二分数N锁相环（用于发射信道）基于相同的参考频率时钟产生第二（发射信道频率）时钟。两个分数N个锁相环共享一个公共的Σ-Δ调制器。因此，可以减小双频合成器的芯片尺寸。

9. 发明授权

US07369001B2 Frequency synthesizer having variable frequency resolution, and fractional-N frequency synthesizing method using sigma-delta modulation of frequency control pulses 有权
$Frequency synthesizer having variable frequency resolution, and fractional-N frequency synthesizing method using sigma-delta modulation of frequency control pulses$
标题翻译：具有可变频率分辨率的频率合成器和使用频率控制脉冲的Σ-Δ调制的分数N频率合成方法
公开(公告)号：US07369001B2
公开(公告)日：2008-05-06
申请号：US11177131
申请日：2005-07-08
申请人： Hwa-Yeal Yu
发明人： Hwa-Yeal Yu
IPC分类号： H03L7/193 , H03M3/00
CPC分类号： H03L7/1976 , H03L7/193
摘要： A fractional-N frequency synthesizer supporting multi-band operation, having variable frequency resolution obtained by sigma-delta modulating a multi-bit frequency resolution control signal having at least one pulse, the at least one pulse having a period of P and a variable duty cycle. Frequency resolution can be increased by changing the duty cycle and without increasing input bits to the sigma-delta modulator. Thus, a core size of the sigma-delta modulator may be reduced.
摘要翻译：一种分数N频率合成器，其支持多频带操作，具有通过Σ-Δ调制获得的可变频率分辨率，该频率分辨率具有至少一个脉冲的多位频率分辨率控制信号，所述至少一个脉冲具有周期P和可变负载周期。可以通过改变占空比并且不增加Σ-Δ调制器的输入位来提高频率分辨率。因此，可以减小Σ-Δ调制器的核心尺寸。

10. 发明申请

US20160111958A1 POWER MANAGEMENT INTEGRATED CIRCUIT FOR SUPPLYING LOAD CURRENT INFORMATION AND ELECTRONIC DEVICE HAVING THE SAME 审中-公开
标题翻译：用于提供负载电流信息的电源管理集成电路和具有该负载电流信息的电子设备
公开(公告)号：US20160111958A1
公开(公告)日：2016-04-21
申请号：US14872285
申请日：2015-10-01
申请人： Minho CHOI , Yus KO , Dongjin KEUM , Hwa Yeal YU , Younghoon LEE
发明人： Minho CHOI , Yus KO , Dongjin KEUM , Hwa Yeal YU , Younghoon LEE
IPC分类号： H02M3/158 , G01R19/00
CPC分类号： H02M3/158 , G01R19/0092 , H02M3/1584 , H02M2001/008
摘要： An electronic device includes a power management integrated circuit (PMIC) including a plurality of regulators. Each of the plurality of regulators has a current meter configured to measure a respective load current. A load device is configured to receive real-time load current information from the PMIC and to perform a performance improvement operation based on the real-time load current information.
摘要翻译：电子设备包括包括多个调节器的功率管理集成电路（PMIC）。多个调节器中的每一个具有被配置为测量相应的负载电流的电流计。负载设备被配置为从PMIC接收实时负载电流信息，并且基于实时负载电流信息执行性能改进操作。

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