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1. 发明授权

US08395950B2 Memory device having a clock skew generator 有权
标题翻译：具有时钟偏移发生器的存储器件
公开(公告)号：US08395950B2
公开(公告)日：2013-03-12
申请号：US12968582
申请日：2010-12-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
IPC分类号： G11C7/00
CPC分类号： G11C7/222
摘要： A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.
摘要翻译：存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的加载。

2. 发明授权

US09099199B2 Memory cell and memory array 有权
标题翻译：存储单元和存储器阵列
公开(公告)号：US09099199B2
公开(公告)日：2015-08-04
申请号：US13420931
申请日：2012-03-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/41 , G11C11/412
摘要： A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.
摘要翻译：存储器单元包括第一，第二和第三列器件。第一列器件包括第一下拉晶体管，第二下拉晶体管，第一开关和第二开关。第二列器件包括第三下拉晶体管，第四下拉晶体管，第三开关和第四开关。第三列器件包括第一上拉晶体管和第二上拉晶体管。第一上拉晶体管，第一下拉晶体管和第三下拉晶体管作为第一反相器连接，第二上拉晶体管，第二下拉晶体管和第四下拉晶体管作为第二反相器连接。第一个反相器和第二个反相器是交叉耦合的。第一开关，第二开关，第三开关和第四开关与第一和第二逆变器的输出端子耦合。

3. 发明授权

US08773930B2 Built-in test circuit and method 有权
标题翻译：内置测试电路及方法
公开(公告)号：US08773930B2
公开(公告)日：2014-07-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

4. 发明申请

US20130201776A1 BUILT-IN TEST CIRCUIT AND METHOD 有权
标题翻译：内置测试电路和方法
公开(公告)号：US20130201776A1
公开(公告)日：2013-08-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

5. 发明授权

US08693265B2 Data inversion for dual-port memory 有权
标题翻译：双端口存储器的数据反转
公开(公告)号：US08693265B2
公开(公告)日：2014-04-08
申请号：US13552692
申请日：2012-07-19
申请人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
发明人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/1075 , G11C8/16 , G11C11/412
摘要： A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.
摘要翻译：半导体存储器包括每个包括第一和第二端口的第一和第二存储器存储器锁存器。第一对位线耦合到第一端口，并且第二对位线耦合到第二端口。第一和第二对位线在第一和第二存储器锁存器之间被扭转。第一读出放大器耦合到第一对位线，用于输出数据，第二读出放大器耦合到第二对位线，用于输出中间数据信号。输出逻辑电路耦合到第二读出放大器的输出，并且被配置为基于中间数据信号和控制信号输出数据，该控制信号识别数据是否正在从第一存储器存储锁存器或第二存储器存储器锁存器中读取。

6. 发明授权

US08406028B1 Word line layout for semiconductor memory 有权
标题翻译：半导体存储器的字线布局
公开(公告)号：US08406028B1
公开(公告)日：2013-03-26
申请号：US13285212
申请日：2011-10-31
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
IPC分类号： G11C5/06 , H01L21/66
CPC分类号： H01L27/1104 , G11C8/16 , G11C11/412 , H01L27/0207
摘要： A semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.
摘要翻译：半导体存储器包括第一和第二字线。第一类型的第一位单元耦合到多个位线中的第一位，并且具有第一布局，其中第一类型的第一位单元与第一数量的通孔耦合到第一字线，并且第二个字线与第二个通孔。第二类型的第一位单元耦合到多个位线中的第二位，并且具有第二布局，其中第二类型的第一位单元与第三数量的通孔耦合到第一字线，并且第二个字线，第四个通孔。第一个字线上的负载近似等于第二个字线上的负载。

7. 发明申请

US20100124099A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20100124099A1
公开(公告)日：2010-05-20
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

8. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

9. 发明授权

US08363454B2 SRAM bit cell 有权
标题翻译： SRAM位单元
公开(公告)号：US08363454B2
公开(公告)日：2013-01-29
申请号：US13015773
申请日：2011-01-28
申请人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
发明人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
摘要翻译：半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

10. 发明申请

US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于在半导体器件中形成器件电池的布局方案和方法
公开(公告)号：US20120256235A1
公开(公告)日：2012-10-11
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

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