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1. 发明授权

US08792292B2 Providing row redundancy to solve vertical twin bit failures 有权
标题翻译：提供行冗余来解决垂直双位故障
公开(公告)号：US08792292B2
公开(公告)日：2014-07-29
申请号：US13046625
申请日：2011-03-11
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/846
摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
摘要翻译：电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行地址。第一比较器被配置为接收和比较第一行地址和第三行地址。第二比较器被配置为接收和比较第二行地址和第三行地址。第一行地址和第二行地址是存储器中的失败行地址。

2. 发明申请

US20120230127A1 Providing Row Redundancy to Solve Vertical Twin Bit Failures 有权
标题翻译：提供行冗余来解决垂直双位错误
公开(公告)号：US20120230127A1
公开(公告)日：2012-09-13
申请号：US13046625
申请日：2011-03-11
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C29/04
CPC分类号： G11C29/846
摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
摘要翻译：电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行地址。第一比较器被配置为接收和比较第一行地址和第三行地址。第二比较器被配置为接收和比较第二行地址和第三行地址。第一行地址和第二行地址是存储器中的失败行地址。

3. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

4. 发明申请

US20130094307A1 BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN 有权
标题翻译：用于低功率存储器设计的位线电压偏置
公开(公告)号：US20130094307A1
公开(公告)日：2013-04-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

5. 发明授权

US08982609B2 Memory having read assist device and method of operating the same 有权
标题翻译：具有读取辅助装置的存储器及其操作方法
公开(公告)号：US08982609B2
公开(公告)日：2015-03-17
申请号：US13372099
申请日：2012-02-13
申请人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
发明人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/4094 , G11C11/419
摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
摘要翻译：存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

6. 发明授权

US09153302B2 Memory and method of operating the same 有权
标题翻译：内存和操作方法相同
公开(公告)号：US09153302B2
公开(公告)日：2015-10-06
申请号：US13362847
申请日：2012-01-31
申请人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
发明人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
IPC分类号： G11C7/00 , G11C7/12 , G11C7/18 , G11C11/419
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
摘要翻译：存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。每个存储块包括一对位线和耦合到该对位线的多个存储器单元。每个全局位线耦合到至少一个存储器块。预充电电路被配置为将全局位线一次一个地预充电到预充电电压。选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。

7. 发明授权

US08659090B2 Resistive memory and methods for forming the same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US08659090B2
公开(公告)日：2014-02-25
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

8. 发明申请

US20130161707A1 Resistive Memory and Methods for Forming the Same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US20130161707A1
公开(公告)日：2013-06-27
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

9. 发明授权

US08976611B2 Asymmetric sensing amplifier, memory device and designing method 有权
标题翻译：非对称感测放大器，存储器件及设计方法
公开(公告)号：US08976611B2
公开(公告)日：2015-03-10
申请号：US13837614
申请日：2013-03-15
申请人： Jung-Ping Yang , Chia-En Huang , Fu-An Wu , Chih-Chieh Chiu , Cheng Hung Lee
发明人： Jung-Ping Yang , Chia-En Huang , Fu-An Wu , Chih-Chieh Chiu , Cheng Hung Lee
IPC分类号： G11C7/00 , G11C7/06 , G06F17/50 , G11C7/10 , G11C7/12 , G11C11/419
CPC分类号： G11C7/065 , G06F17/5063 , G06F17/5081 , G11C7/1048 , G11C7/12 , G11C11/419
摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要翻译：用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。第一和第二节点分别耦合到第一和第二位线。输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流响应于从存储器单元读出的第二数据的电压。输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。第一个电流大于第二个电流。

10. 发明授权

US08385136B2 Memory circuit and method of operating the same 有权
标题翻译：存储电路及其操作方法
公开(公告)号：US08385136B2
公开(公告)日：2013-02-26
申请号：US12913087
申请日：2010-10-27
申请人： Cheng Hung Lee , Jung-Ping Yang
发明人： Cheng Hung Lee , Jung-Ping Yang
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C7/067
摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.
摘要翻译：本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。

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