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1. 发明授权

US08410573B2 SOI (silicon on insulator) structure semiconductor device and method of manufacturing the same 有权
标题翻译： SOI（绝缘体上硅）结构半导体器件及其制造方法
公开(公告)号：US08410573B2
公开(公告)日：2013-04-02
申请号：US12734240
申请日：2008-10-20
申请人： Hiroshi Ohtsuki , Mitsutaka Katada , Nobuhiko Noto , Hiroshi Takeno , Kazuhiko Yoshida
发明人： Hiroshi Ohtsuki , Mitsutaka Katada , Nobuhiko Noto , Hiroshi Takeno , Kazuhiko Yoshida
IPC分类号： H01L29/06
CPC分类号： H01L29/78609 , H01L21/26506 , H01L21/3221 , H01L21/3223 , H01L21/3226 , H01L21/76256 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/32 , H01L29/7849 , H01L29/78603
摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
摘要翻译：在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。晶格畸变层能够用作吸杂位点。调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

2. 发明授权

US07985660B2 Method for manufacturing soi wafer 有权
标题翻译：制造硅片的方法
公开(公告)号：US07985660B2
公开(公告)日：2011-07-26
申请号：US12450960
申请日：2008-04-16
申请人： Isao Yokokawa , Hiroshi Takeno , Nobuhiko Noto
发明人： Isao Yokokawa , Hiroshi Takeno , Nobuhiko Noto
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76256
摘要： The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p+ silicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer. As a result, it is possible to provide the method for manufacturing an SOI wafer which can easily prevent the p-type dopant contained in the base wafer from outwardly diffusing from the surface on the opposite side of the bonding surface of the base wafer due to a high-temperature heat treatment, suppress this dopant from being mixed into the SOI layer, and reduce warpage.
摘要翻译：本发明提供一种制造SOI晶片的方法，包括：准备由p +硅单晶晶片构成的基底晶片和由含有掺杂剂的硅单晶晶片组成的接合晶片的步骤，其浓度低于基片; 基于热氧化在基底晶片的整个表面上形成氧化硅膜的步骤; 通过氧化硅膜将接合晶片接合到基底晶片的步骤; 以及减小接合晶片的厚度以形成SOI层的步骤，其中在所述基底晶片的接合表面的相反侧的表面上形成CVD绝缘膜的步骤在所述基底晶片的接合表面的热氧化步骤之前提供基片。结果，可以提供一种制造SOI晶片的方法，其可以容易地防止基底晶片中包含的p型掺杂物从基底晶片的接合表面的相对侧上的表面向外扩散，这是由于进行高温热处理，可以抑制该掺杂剂混入SOI层，从而降低翘曲。

3. 发明申请

US20100264510A1 SOI (SILICON ON INSULATOR) STRUCTURE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： SOI（绝缘体硅）结构半导体器件及其制造方法
公开(公告)号：US20100264510A1
公开(公告)日：2010-10-21
申请号：US12734240
申请日：2008-10-20
申请人： Hiroshi Ohtsuki , Mitsutaka Katada , Nobuhiko Noto , Hiroshi Takeno , Kazuhiko Yoshida
发明人： Hiroshi Ohtsuki , Mitsutaka Katada , Nobuhiko Noto , Hiroshi Takeno , Kazuhiko Yoshida
IPC分类号： H01L29/06 , H01L21/306
CPC分类号： H01L29/78609 , H01L21/26506 , H01L21/3221 , H01L21/3223 , H01L21/3226 , H01L21/76256 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/32 , H01L29/7849 , H01L29/78603
摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
摘要翻译：在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。晶格畸变层能够用作吸杂位点。调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

4. 发明授权

US5598452A Method of evaluating a silicon single crystal 失效
标题翻译：评估硅单晶的方法
公开(公告)号：US5598452A
公开(公告)日：1997-01-28
申请号：US524453
申请日：1995-09-06
申请人： Hiroshi Takeno , Ryoji Hoshi , Satoshi Ushio , Takao Takenaka
发明人： Hiroshi Takeno , Ryoji Hoshi , Satoshi Ushio , Takao Takenaka
IPC分类号： G01N23/207 , H01L21/66
CPC分类号： G01N23/207
摘要： According to the invention, it is sought to provide a method of evaluating single crystal of silicon, which permits determination of the amount of precipitated oxygen of even a sample having been heat treated and with unknown initial interstitial oxygen concentration. X-rays radiated from X-ray source 7 is converted by slit 6 into a thin, parallel incident X-ray beam 3 to be incident on sample single crystal 1. After adjusting the angle .theta.1 of sample with respect to the incident X-ray beam such as to satisfy Bragg conditions, diffracted X-rays 4 produced by diffraction on the sample single crystal 1 are coupled from the back side thereof through X-ray receiving slit 8 to scintillator 5 for intensity measurement. The amount of precipitated oxygen is calculated from the measured diffracted X-ray intensity.
摘要翻译：根据本发明，寻求提供一种评估硅单晶的方法，其允许确定即使经热处理的样品和未知的初始间隙氧浓度的沉淀氧的量。从X射线源7辐射的X射线被狭缝6转换为薄的平行的入射X射线束3，以入射到样品单晶1上。在调整样品相对于入射X射线的角度θ1后，例如为了满足布拉格条件，由样品单晶1衍射产生的衍射X射线4从背面通过X射线接收狭缝8耦合到用于强度测量的闪烁体5。从测量的衍射X射线强度计算沉淀氧的量。

5. 发明授权

US08268705B2 Method for producing SOI wafer 有权
标题翻译：制造SOI晶圆的方法
公开(公告)号：US08268705B2
公开(公告)日：2012-09-18
申请号：US12226264
申请日：2007-04-23
申请人： Kazuhiko Yoshida , Masao Matsumine , Hiroshi Takeno
发明人： Kazuhiko Yoshida , Masao Matsumine , Hiroshi Takeno
IPC分类号： H01L21/322
CPC分类号： H01L21/76256 , H01L21/26506 , H01L21/26533 , H01L21/3226
摘要： The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.
摘要翻译：本发明是一种制造SOI晶片的方法，其至少包括通过离子注入从基底晶片或接合晶片的一个表面在硅中电惰性的中性元件形成离子注入损伤层的步骤，其中离子以1×10 12原子/ cm 2以上且小于1×10 15原子/ cm 2的剂量进行形成离子注入损伤层的工序。结果，可以提供一种制造具有足够的吸气能力的SOI晶片的方法，同时提供泄漏故障的抑制，氧化物介质击穿电压的劣化等。

6. 发明申请

US20100323502A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20100323502A1
公开(公告)日：2010-12-23
申请号：US12449347
申请日：2008-02-19
申请人： Hiroshi Takeno , Tohru Ishizuka , Nobuhiko Noto
发明人： Hiroshi Takeno , Tohru Ishizuka , Nobuhiko Noto
IPC分类号： H01L21/762
CPC分类号： H01L21/76243 , H01L21/26533
摘要： The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
摘要翻译：本发明提供一种SOI衬底的制造方法，其至少包括：从单晶硅衬底的一个主表面离子注入氧离子以形成氧离子注入层的氧离子注入步骤; 以及对其中形成有氧离子注入层的单晶硅衬底进行热处理以将氧离子注入层改变为掩埋氧化膜层的热处理步骤，其中用于氧离子注入的加速能为预先根据要获得的掩埋氧化物膜层的厚度确定，并且用所确定的加速能量进行氧离子注入步骤以制造SOI衬底。由此，能够提供能够高效地制造具有连续均匀的薄埋氧化膜层的SOI衬底的SOI衬底制造方法。

7. 发明授权

US07799660B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US07799660B2
公开(公告)日：2010-09-21
申请号：US12078526
申请日：2008-04-01
申请人： Tohru Ishizuka , Hiroshi Takeno , Nobuhiko Noto
发明人： Tohru Ishizuka , Hiroshi Takeno , Nobuhiko Noto
IPC分类号： H01L21/322
CPC分类号： H01L21/76243 , H01L21/26533 , H01L21/3226
摘要： The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a buried oxide film layer is performed with respect to the single-crystal silicon substrate to manufacture the SOI substrate, the method comprising: implanting a neutral element ion having a dose amount of 1×1012 atoms/cm2 or above and less than 1×1015 atoms/cm2 into a back surface to form an ion-implanted damage layer after performing the oxide film-forming heat treatment; and gettering a metal impurity in the ion-implanted damage layer by a subsequent heat treatment to enable reducing a metal impurity concentration on a front surface side. Thereby, there is provided a method for manufacturing an SOI substrate having a gettering layer on a back surface thereof in a simple process at a low cost.
摘要翻译：本发明提供了一种用于制造SOI衬底的方法，通过该SOI衬底从单晶硅衬底的至少一个主表面注入氧离子以形成氧离子注入层，然后进行氧化膜形成热处理相对于单晶硅基板进行将形成的氧离子注入层变成埋入氧化膜层的方法，制造SOI衬底，该方法包括：注入剂量为1×1012的中性元素离子原子/ cm 2以上且小于1×10 15原子/ cm 2进入背面，在进行氧化膜形成热处理后形成离子注入损伤层; 并通过随后的热处理在离子注入的损伤层中吸收金属杂质，以减少前表面侧的金属杂质浓度。因此，提供了一种以简单的方法以低成本制造其背面上具有吸气层的SOI衬底的方法。

8. 发明申请

US20090104752A1 Method for Producing Soi Wafer 有权
标题翻译：生产硅晶片的方法
公开(公告)号：US20090104752A1
公开(公告)日：2009-04-23
申请号：US12226544
申请日：2007-04-16
申请人： Kazuhiko Yoshida , Masao Matsumine , Hiroshi Takeno
发明人： Kazuhiko Yoshida , Masao Matsumine , Hiroshi Takeno
IPC分类号： H01L21/762
CPC分类号： H01L21/76256 , H01L21/26506
摘要： The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.
摘要翻译： SOI晶片的制造方法技术领域本发明涉及一种SOI晶片的制造方法，其特征在于，至少具有通过对通过将基底晶片和接合晶片进行接合而获得的接合晶片进行热处理来提高接合强度的接合热处理的步骤，其中氩是离子至少在接合步骤之前，以1×10 15个原子/ cm 2或更大的剂量从基片或接合晶片的表面注入，在接合步骤中使用离子注入氩的表面作为接合表面，并且接合热处理的处理温度的升温速度为5℃/分钟以上。因此，本发明提供了一种用于制造SOI晶片的方法，其有助于SOI掩模的有效生产，该SOI晶片在其绝缘体层附近具有均匀导入的多晶硅层，并且对SOI层中的金属污染具有高吸杂能力通过简单而低成本的方法。

9. 发明授权

US07311888B2 Annealed wafer and method for manufacturing the same 有权
标题翻译：退火晶片及其制造方法
公开(公告)号：US07311888B2
公开(公告)日：2007-12-25
申请号：US10530557
申请日：2003-09-29
申请人： Hiroshi Takeno , Masahiro Sakurada , Takeshi Kobayashi
发明人： Hiroshi Takeno , Masahiro Sakurada , Takeshi Kobayashi
IPC分类号： C30B15/20 , C23C33/36
CPC分类号： C30B33/02 , C30B29/06 , H01L21/3225
摘要： The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 μm from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×109/cm3.
摘要翻译：本发明提供了一种退火晶片，其具有用作器件制造区域的晶片表面层并且具有优异的氧化膜介电击穿特性，以及晶片本体层，其中氧化物沉淀物以高密度存在于晶片前的阶段被加载到器件制造工艺中以提供优异的IG能力，以及用于制造退火晶片的方法。本发明涉及通过对由通过切克劳斯基法生长的硅单晶制造的硅晶片进行热处理而获得的退火晶片，其中在具有至少一深度的区域中的氧化膜介电击穿特性的良好的芯片产量从晶片表面达到5μm的母体的密度为95％以上，并且在晶片体中可检测到的氧化物析出物的密度和每个具有不小于显示吸气能力的尺寸的尺寸不小于1×10 9 / SUP> / cm 3。

10. 发明授权

US07229501B2 Silicon epitaxial wafer and process for manufacturing the same 有权
标题翻译：硅外延晶片及其制造方法
公开(公告)号：US07229501B2
公开(公告)日：2007-06-12
申请号：US10501672
申请日：2003-01-17
申请人： Hiroshi Takeno
发明人： Hiroshi Takeno
IPC分类号： C30B25/12
CPC分类号： H01L21/3225
摘要： The present invention provides a silicon epitaxial wafer having an excellent IG capability all over the radial direction thereof and a process for manufacturing the same. The present invention is directed to a silicon epitaxial wafer having an excellent gettering capability all over the radial direction thereof, wherein density of oxide precipitates detectable in the interior of a silicon single crystal substrate after epitaxial growth is 1×109/cm3 or higher at any position in the radial direction.
摘要翻译：本发明提供了在其半径方向上具有优异的IG能力的硅外延晶片及其制造方法。本发明涉及一种在其径向上具有优异的吸气能力的硅外延晶片，其中在外延生长之后在硅单晶衬底的内部可检测到的氧化物沉淀物的密度为1×10 9 / cm 3以上的任意位置。

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