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1. 发明申请

US20120246601A1 PATTERN CORRECTING METHOD, MASK FORMING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：图案校正方法，掩模形成方法和制造半导体器件的方法
公开(公告)号：US20120246601A1
公开(公告)日：2012-09-27
申请号：US13237435
申请日：2011-09-20
申请人： Masanari KAJIWARA , Toshiya KOTANI , Sachiko KOBAYASHI , Hiromitsu MASHITA , Fumiharu NAKAJIMA
发明人： Masanari KAJIWARA , Toshiya KOTANI , Sachiko KOBAYASHI , Hiromitsu MASHITA , Fumiharu NAKAJIMA
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , G03F7/70441
摘要： A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.
摘要翻译：实施例的图案校正方法在形成有衬底图案的情况下，在成为误差图案的位置附近的电路图案的设计布局上计算图案覆盖率的分布。然后，通过添加加法图案，设置图案覆盖物的分布差异变小的设计布局上的区域作为附加区域。接下来，生成要添加到相加区域的添加模式候选，并根据预定的选择标准从候选中选择要添加到设计布局的添加模式，并将添加模式添加到添加区域。

2. 发明授权

US08183148B2 Method of fabricating semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US08183148B2
公开(公告)日：2012-05-22
申请号：US12542540
申请日：2009-08-17
申请人： Ryota Aburada , Hiromitsu Mashita , Toshiya Kotani , Chikaaki Kodama
发明人： Ryota Aburada , Hiromitsu Mashita , Toshiya Kotani , Chikaaki Kodama
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
摘要翻译：根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割第一种模式

3. 发明授权

US08146022B2 Mask pattern data generation method, mask manufacturing method, semiconductor device manufacturing method, and pattern data generation program 有权
标题翻译：掩模图案数据生成方法，掩模制造方法，半导体器件制造方法和图案数据生成程序
公开(公告)号：US08146022B2
公开(公告)日：2012-03-27
申请号：US12409068
申请日：2009-03-23
申请人： Hiromitsu Mashita , Toshiya Kotani , Takashi Obara
发明人： Hiromitsu Mashita , Toshiya Kotani , Takashi Obara
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G03F1/36
摘要： According to an aspect of the present invention, there is provided a mask pattern data generation method including: a first step of obtaining a mask data representing from a design pattern by performing a process simulation with a process parameter having a first value; a second step of obtaining a finished pattern from the mask data by performing the process simulation with the process parameter having a different value; a third step of verifying whether a dimensional error therebetween is within an allowable range; and a fourth step of: if the dimensional error is within the allowable range, determining the mask pattern data; and if the dimensional error is not within the allowable range, repeating the above steps by updating the process parameter until the dimensional error becomes within the allowable range.
摘要翻译：根据本发明的一个方面，提供了一种掩模图案数据生成方法，包括：第一步骤，通过利用具有第一值的处理参数进行处理模拟来获得表示设计图案的掩模数据; 通过使用具有不同值的处理参数进行处理模拟从掩模数据获得完成图案的第二步骤; 验证其间的尺寸误差是否在允许范围内的第三步骤; 以及第四步骤：如果所述尺寸误差在所述容许范围内，则确定所述掩模图案数据; 并且如果尺寸误差不在允许范围内，则通过更新处理参数重复上述步骤，直到尺寸误差变得在允许范围内。

4. 发明授权

US08108824B2 Pattern verification method, method of manufacturing semiconductor device, and recording media 失效
标题翻译：模式验证方法，制造半导体器件的方法和记录介质
公开(公告)号：US08108824B2
公开(公告)日：2012-01-31
申请号：US12420931
申请日：2009-04-09
申请人： Toshiya Kotani , Hiromitsu Mashita , Kazuhito Kobayashi
发明人： Toshiya Kotani , Hiromitsu Mashita , Kazuhito Kobayashi
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.
摘要翻译：根据实施例的图案验证方法包括：将基于图案数据形成的图案数据区域或图案形成区域划分为多个单位区域，计算相对于每个单位区域的图案面积比，计算量的差异每个单位区域与相邻单位区域之间的图案面积比率，将测量点的数量或密度相对于每个单位区域设置为图案数据区域或图案形成区域的图案，根据测量每个测量点处的图案尺寸，以及验证尺寸测量值是否在预定范围内。

5. 发明申请

US20110047518A1 PATTERN DETERMINING METHOD 审中-公开
标题翻译：图案确定方法
公开(公告)号：US20110047518A1
公开(公告)日：2011-02-24
申请号：US12860278
申请日：2010-08-20
申请人： Issui Aiba , Takafumi Taguchi , Hiromitsu Mashita , Taiga Uno , Fumiharu Nakajima , Toshiya Kotani , Tadahito Fujisawa
发明人： Issui Aiba , Takafumi Taguchi , Hiromitsu Mashita , Taiga Uno , Fumiharu Nakajima , Toshiya Kotani , Tadahito Fujisawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area.
摘要翻译：根据实施例，在处理图案之前的处理中形成的图案上的轮廓图案数据上设置第一代表点。然后，计算从第一代表点到外围图案的最小距离。然后，计算出与第一代表点和外围图案夹着的没有图案的区域的区域在距离第一代表点的预定范围内的区域中。然后，通过使用最小距离和面积确定第一代表点是否变为处理失败。

6. 发明授权

US07713833B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07713833B2
公开(公告)日：2010-05-11
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

7. 发明申请

US20100035168A1 PATTERN PREDICTING METHOD, RECORDING MEDIA AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：图案预测方法，记录介质和制造半导体器件的方法
公开(公告)号：US20100035168A1
公开(公告)日：2010-02-11
申请号：US12537934
申请日：2009-08-07
申请人： Fumiharu NAKAJIMA , Toshiya Kotani , Hiromitsu Mashita , Chikaaki Kodama
发明人： Fumiharu NAKAJIMA , Toshiya Kotani , Hiromitsu Mashita , Chikaaki Kodama
IPC分类号： G03F7/00
CPC分类号： G03F7/70625 , G03F1/36 , G03F1/68
摘要： A pattern predicting method according to one embodiment includes obtaining shape data of a target pattern from shape data of a second pattern to be formed by transferring a first pattern at predetermined process conditions by using a first neutral network, the target pattern being to be a target of the second pattern when the first pattern is transferred at the predetermined process conditions, so as to keep the transferred patterns within an acceptable range, the transferred patterns being formed by transferring the first pattern at process conditions changed from the predetermined process conditions and obtaining shape data of a new first pattern for forming the target pattern at the predetermined process conditions by using a second neutral network.
摘要翻译：根据一个实施例的图案预测方法包括通过使用第一中性网络在预定处理条件下传送第一图案而形成的第二图案的形状数据的目标图案的形状数据，目标图案为目标当第一图案在预定工艺条件下被转印时，以便将转印图案保持在可接受的范围内，通过在从预定工艺条件变化的工艺条件下转印第一图案形成转印图案并获得形状通过使用第二中性网络在预定处理条件下形成目标图案的新的第一图案的数据。

8. 发明申请

US20090239177A1 MASK PATTERN DATA GENERATION METHOD, MASK MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND PATTERN DATA GENERATION PROGRAM 有权
标题翻译：掩模图形数据生成方法，掩模制造方法，半导体器件制造方法和图案数据生成程序
公开(公告)号：US20090239177A1
公开(公告)日：2009-09-24
申请号：US12409068
申请日：2009-03-23
申请人： Hiromitsu MASHITA , Toshiya Kotani , Takashi Obara
发明人： Hiromitsu MASHITA , Toshiya Kotani , Takashi Obara
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F1/36
摘要： According to an aspect of the present invention, there is provided a mask pattern data generation method including: a first step of obtaining a mask data representing from a design pattern by performing a process simulation with a process parameter having a first value; a second step of obtaining a finished pattern from the mask data by performing the process simulation with the process parameter having a different value; a third step of verifying whether a dimensional error therebetween is within an allowable range; and a fourth step of: if the dimensional error is within the allowable range, determining the mask pattern data; and if the dimensional error is not within the allowable range, repeating the above steps by updating the process parameter until the dimensional error becomes within the allowable range.
摘要翻译：根据本发明的一个方面，提供了一种掩模图案数据生成方法，包括：第一步骤，通过利用具有第一值的处理参数进行处理模拟来获得表示设计图案的掩模数据; 通过使用具有不同值的处理参数进行处理模拟从掩模数据获得完成图案的第二步骤; 验证其间的尺寸误差是否在允许范围内的第三步骤; 以及第四步骤：如果所述尺寸误差在所述容许范围内，则确定所述掩模图案数据; 并且如果尺寸误差不在允许范围内，则通过更新处理参数重复上述步骤，直到尺寸误差变得在允许范围内。

9. 发明申请

US20060157833A1 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device 失效
标题翻译：半导体器件，制造图案布局的方法，制造掩模图案的方法，制作布局的方法，制造光掩模的方法，光掩模和半导体器件的制造方法
公开(公告)号：US20060157833A1
公开(公告)日：2006-07-20
申请号：US11299843
申请日：2005-12-13
申请人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L21/50 , H01L23/02
CPC分类号： H01L27/0207 , G03F1/00 , G03F1/36 , G06F17/5068 , H01L27/115 , H01L27/11517 , H01L27/11519
摘要： A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
摘要翻译：半导体器件包括半导体衬底和在半导体衬底上至少包括N（> = 2）个电路图案的电路图案组，至少N个电路图案中的至少一个端部附近包括电连接区域连接到与电路图案组不同的另一个电路图案组中的电路图案，所述至少N个配线图案包括电路图案N 1和至少一个电路图案Ni（i> = 2），该电路图案沿纵向方向电路图案N 1的至少一个电路图案Ni具有较大的i被布置在远离电路图案N 1的更远位置处，并且根据包括至少Ni电路图案中的连接区域的图案， i越大，连接区域被设置在纵向方向上的另一位置。

10. 发明授权

US08336005B2 Pattern dimension calculation method and computer program product 有权
标题翻译：图案尺寸计算方法和计算机程序产品
公开(公告)号：US08336005B2
公开(公告)日：2012-12-18
申请号：US13050864
申请日：2011-03-17
申请人： Takafumi Taguchi , Toshiya Kotani , Hiromitsu Mashita , Fumiharu Nakajima , Ryota Aburada , Chikaaki Kodama
发明人： Takafumi Taguchi , Toshiya Kotani , Hiromitsu Mashita , Fumiharu Nakajima , Ryota Aburada , Chikaaki Kodama
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.
摘要翻译：根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。

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