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1. 发明授权

US5929482A Power semiconductor device and method for manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US5929482A
公开(公告)日：1999-07-27
申请号：US61056
申请日：1998-04-16
申请人： Minoru Kawakami , Mitsuhiro Yano , Yasunori Yamashita , Hidetoshi Souno
发明人： Minoru Kawakami , Mitsuhiro Yano , Yasunori Yamashita , Hidetoshi Souno
IPC分类号： H01L29/36 , H01L21/28 , H01L21/308 , H01L21/322 , H01L21/336 , H01L29/78 , H01L21/324
CPC分类号： H01L21/3083 , H01L29/7813 , H01L21/28167
摘要： An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device. With this structure, it is possible to reduce a leak current, prevent deterioration in main breakdown voltage and stabilize gate-oxide-film breakdown-voltage characteristics in a vertical MOSFET with trench gate.
摘要翻译：使用硅晶片作为基材并且包括As的n +半导体衬底（1）包括浓度在12E17原子/ cm3至20E17原子/ cm3范围内的氧。在半导体衬底（1）的第二主表面（1S2）上依次形成n型第一外延生长层（2）和p型扩散层（3）。外延生长层（10）的厚度设定为20μm以下。沟槽（6）形成为从扩散层（3）的表面延伸到第一外延生长层（2）的内部。在沟槽（6）的底表面（6B）和壁表面（6W）上形成栅极氧化膜（5），并且导电层（11）填充沟槽（6）。在沟槽（6）的拐角（6C）处形成n型源极层（4）。之后，形成预定的电极等，以完成装置。利用这种结构，可以减小泄漏电流，防止主要击穿电压的劣化并且在具有沟槽栅极的垂直MOSFET中稳定栅极氧化膜击穿电压特性。

2. 发明授权

US06285058B1 Insulated gate semiconductor device and method of manufacturing the same 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：US06285058B1
公开(公告)日：2001-09-04
申请号：US09485702
申请日：2000-02-28
申请人： Atsushi Narazaki , Hidetoshi Souno , Yasunori Yamashita
发明人： Atsushi Narazaki , Hidetoshi Souno , Yasunori Yamashita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4238
摘要： The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (9), (10) and (13) are provided to keep away from an upper end (UE) of an edge of a gate trench (6) along its longitudinal direction. More specifically, the gate wiring (9) coupled integrally with an upper surface of a gate electrode (7) is formed apart from the upper end (UE) and the gate wiring (10) is formed on an insulating film (4) also apart from the upper end (UE). The two gate wirings (9) and (10) are connected to each other through the gate wiring (13) formed on a BPSG layer (11). Moreover, an upper face of the gate electrode (7) is positioned on the same level as an upper main surface of a semiconductor substrate (90) or therebelow in the vicinity of the upper end (UE). Consequently, a concentration of an electric field generated in insulating films (8) and (17) covering the upper end (UE) can be relieved or eliminated.
摘要翻译：绝缘栅半导体器件及其制造方法技术领域本发明涉及绝缘栅半导体器件及其制造方法，更具体地，涉及提高栅极击穿电压的改进。为了实现该目的，提供了栅极布线（9），（10）和（13）以沿着其纵向方向远离栅极沟槽（6）的边缘的上端（UE）。更具体地，与栅电极（7）的上表面一体地结合的栅极布线（9）形成为与上端（UE）分开，并且栅极布线（10）也形成在也分开的绝缘膜（4）上来自上端（UE）。两个栅极布线（9）和（10）通过形成在BPSG层（11）上的栅极布线（13）相互连接。此外，栅电极（7）的上表面位于与半导体衬底（90）的上主表面或其上端附近相同的高度。因此，可以减轻或消除在覆盖上端（UE）的绝缘膜（8）和（17）中产生的电场的浓度。

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