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1. 发明授权

US08112034B2 Method and system for using PSK sync word for fine tuning frequency adjustment 有权
标题翻译：使用PSK同步字进行微调频率调整的方法和系统
公开(公告)号：US08112034B2
公开(公告)日：2012-02-07
申请号：US12052214
申请日：2008-03-20
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
IPC分类号： H04B7/00
CPC分类号： H04L25/063 , H04L27/22 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种使用相移键（PSK）同步字进行微调频率调整的方法和系统。本发明的一个方面提供了当在执行粗频率偏移调整之后剩余DC偏移保留时，调整射频（RF）接收机中的本地振荡器频率。由于蓝牙分组的基于PSK的调制部分所需的同步，因此可能需要进行微调。在蓝牙分组的同步序列部分中检测到的残余相移可用于确定残差或精细频率调整。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

2. 发明申请

US20090093224A1 Translational loop transmitter architecture employing channel power ratio measurements for modulation accuracy calibration 有权
公开(公告)号：US20090093224A1
公开(公告)日：2009-04-09
申请号：US12336830
申请日：2008-12-17
申请人： Hong Shi , Henrik Tholstrup Jensen
发明人： Hong Shi , Henrik Tholstrup Jensen
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The IF modulator receives a modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope. The envelope time delay adjust block receives an envelope signal corresponding to the original modulated signal and produces a time delayed envelope signal based upon a time delay control signal. The envelope adjust block adjusts the modulated RF signal based upon the time delayed envelope signal to produce an envelope adjusted modulated RF signal. Finally, the time delay calibration block receives the envelope adjusted modulated RF signal and produces the time delay control signal.

3. 发明申请

US20130002317A1 DIGITAL PHASE LOCKED LOOP CIRCUITS WITH MULTIPLE DIGITAL FEEDBACK LOOPS 有权
标题翻译：数字相位锁定电路与多个数字反馈灯
公开(公告)号：US20130002317A1
公开(公告)日：2013-01-03
申请号：US13173694
申请日：2011-06-30
申请人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
发明人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/18
摘要： Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
摘要翻译：具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出通过输入参考时钟信号和第一反馈时钟信号之间的时间差。提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

4. 发明申请

US20120319774A1 MULTI-STAGE GAIN CONTROL IN RECEIVERS AND OTHER CIRCUITS 有权
标题翻译：接收机和其他电路的多级增益控制
公开(公告)号：US20120319774A1
公开(公告)日：2012-12-20
申请号：US13164739
申请日：2011-06-20
申请人： Amir Ibrahim , Henrik Tholstrup Jensen , Shahla Khorram , Aminghasem Safarian , Seema Anand
发明人： Amir Ibrahim , Henrik Tholstrup Jensen , Shahla Khorram , Aminghasem Safarian , Seema Anand
IPC分类号： H03G3/20
CPC分类号： H03G3/3068 , H03D3/009 , H04B1/28
摘要： Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively.
摘要翻译：公开了技术和设备以在具有两级或更多级信号放大的电路或器件中提供多级增益控制。具有多级增益控制的电路可以包括耦合以接收输入信号并产生放大的输出信号的放大级。每个放大级包括增益可调节的放大器和被耦合以测量放大器的输出信号并产生指示放大器的输出信号的信号强度的检测器信号的信号检测器。耦合增益控制电路以分别从放大级中的信号检测器接收检测器信号，并且分别基于相应的接收到的检测器信号来控制放大级的放大器的增益。

5. 发明申请

US20100009673A1 METHOD AND SYSTEM FOR FREQUENCY FEEDBACK ADJUSTMENT IN DIGITAL RECEIVERS 有权
标题翻译：数字接收机频率反馈调整方法与系统
公开(公告)号：US20100009673A1
公开(公告)日：2010-01-14
申请号：US12563765
申请日：2009-09-21
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
IPC分类号： H04W24/00
CPC分类号： H03J7/02 , H03J2200/02 , H04L25/063 , H04L27/142 , H04L2027/0057 , H04L2027/0065
摘要： In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by, for example, utilizing a header portion of a packet communicated via a wireless interface. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种用于数字接收机中的频率反馈调整的方法和系统。 DC偏移可能由RF发射机和RF接收机之间的频率差引起。接收机频率的调整可以在同步发生之后实现，并且可以通过例如利用经由无线接口传送的分组的报头部分来执行。当频率差超过阈值时，可以进行调整。在另一方面，可以通过修改和/或改变锁相环（PLL）微调寄存器来调整RF接收机的频率。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

6. 发明申请

US20080214112A1 Method and System for Using PSK Sync Word for Fine Tuning Frequency Adjustment 有权
标题翻译：使用PSK Sync Word进行微调频率调整的方法和系统
公开(公告)号：US20080214112A1
公开(公告)日：2008-09-04
申请号：US12052214
申请日：2008-03-20
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
IPC分类号： H04B7/00 , H04B1/16
CPC分类号： H04L25/063 , H04L27/22 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种使用相移键（PSK）同步字进行微调频率调整的方法和系统。本发明的一个方面提供了当在执行粗频率偏移调整之后剩余DC偏移保留时，调整射频（RF）接收机中的本地振荡器频率。由于蓝牙分组的基于PSK的调制部分所需的同步，因此可能需要进行微调。在蓝牙分组的同步序列部分中检测到的残余相移可用于确定残差或精细频率调整。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

7. 发明申请

US20120326904A1 MULTI-MODE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：多模式模拟数字转换器
公开(公告)号：US20120326904A1
公开(公告)日：2012-12-27
申请号：US13170155
申请日：2011-06-27
申请人： Henrik Tholstrup Jensen , Jianhua Gan , Seema Anand , Aminghasem Safarian
发明人： Henrik Tholstrup Jensen , Jianhua Gan , Seema Anand , Aminghasem Safarian
IPC分类号： H03M1/20 , H03M1/12
CPC分类号： H03M1/201 , H03M3/332 , H03M3/396 , H03M3/406 , H03M3/456
摘要： Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.
摘要翻译：技术和设备在两个或多个信号频率或频带上提供模数转换，并可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号接收机应用。

8. 发明授权

US08081714B2 Method and system for reuse of CORDIC in an RF transceiver by reconfiguration in real time 有权
标题翻译： CORDIC在RF收发器中实时重配置的方法和系统
公开(公告)号：US08081714B2
公开(公告)日：2011-12-20
申请号：US10989536
申请日：2004-11-16
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Paul Lettieri , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Paul Lettieri , Siukai Mak
IPC分类号： H04L27/00
CPC分类号： H03D3/006
摘要： Methods and systems for processing an RF signal are disclosed herein. Aspects of the method may comprise utilizing a single input CORDIC and a single output CORDIC for synchronizing and demodulating a received signal, wherein the received signal may comprise one or more bit rates. The received signal may comprise a one megabit per second (Mbps) signal. The single input CORDIC may be configured to operate in a rotating mode and the single output CORDIC may be configured to operate in a rotating mode and/or an arctangent (ARCTAN) mode. A rotated output of the single input CORDIC may be correlated with a phase shift keying (PSK) synchronization (sync) word and a portion of the correlated rotated output of the single input CORDIC may be buffered.
摘要翻译：本文公开了用于处理RF信号的方法和系统。该方法的方面可以包括利用单个输入CORDIC和单个输出CORDIC来同步和解调所接收的信号，其中所接收的信号可以包括一个或多个比特率。所接收的信号可以包括一兆兆比特每秒（Mbps）信号。单输入CORDIC可以被配置为以旋转模式操作，并且单输出CORDIC可以被配置为在旋转模式和/或反正切（ARCTAN）模式下操作。单输入CORDIC的旋转输出可以与相移键控（PSK）同步（sync）字相关，并且单个输入CORDIC的相关旋转输出的一部分可以被缓冲。

9. 发明授权

US08050647B2 Method and system for frequency feedback adjustment in digital receivers 有权
标题翻译：数字接收机频率反馈调整方法及系统
公开(公告)号：US08050647B2
公开(公告)日：2011-11-01
申请号：US12563765
申请日：2009-09-21
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
IPC分类号： H04B1/20
CPC分类号： H03J7/02 , H03J2200/02 , H04L25/063 , H04L27/142 , H04L2027/0057 , H04L2027/0065
摘要： In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by, for example, utilizing a header portion of a packet communicated via a wireless interface. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了用于数字接收机中的频率反馈调整的方法和系统。 DC偏移可能由RF发射机和RF接收机之间的频率差引起。接收机频率的调整可以在同步发生之后实现，并且可以通过例如利用经由无线接口传送的分组的报头部分来执行。当频率差超过阈值时，可以进行调整。在另一方面，可以通过修改和/或改变锁相环（PLL）微调寄存器来调整RF接收机的频率。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

10. 发明授权

US08983418B2 Multi-stage gain control in receivers and other circuits 有权
标题翻译：接收机和其他电路中的多级增益控制
公开(公告)号：US08983418B2
公开(公告)日：2015-03-17
申请号：US13164739
申请日：2011-06-20
申请人： Amir Ibrahim , Henrik Tholstrup Jensen , Shahla Khorram , Aminghasem Safarian , Seema Anand
发明人： Amir Ibrahim , Henrik Tholstrup Jensen , Shahla Khorram , Aminghasem Safarian , Seema Anand
IPC分类号： H04B1/06 , H03G3/30 , H04B1/28 , H03D3/00
CPC分类号： H03G3/3068 , H03D3/009 , H04B1/28
摘要： Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively.
摘要翻译：公开了技术和设备以在具有两级或更多级信号放大的电路或器件中提供多级增益控制。具有多级增益控制的电路可以包括耦合以接收输入信号并产生放大的输出信号的放大级。每个放大级包括增益可调节的放大器和被耦合以测量放大器的输出信号并产生指示放大器的输出信号的信号强度的检测器信号的信号检测器。耦合增益控制电路以分别从放大级中的信号检测器接收检测器信号，并且分别基于相应的接收到的检测器信号来控制放大级的放大器的增益。

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