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1. 发明授权

US08034701B2 Methods of forming recessed gate electrodes having covered layer interfaces 失效
标题翻译：形成具有覆盖层界面的凹陷栅电极的方法
公开(公告)号：US08034701B2
公开(公告)日：2011-10-11
申请号：US12533672
申请日：2009-07-31
申请人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
发明人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
IPC分类号： H01L21/3205
CPC分类号： H01L27/10876 , H01L21/28123 , H01L21/823437 , H01L27/10891 , H01L29/517 , H01L29/66621 , H01L29/7834
摘要： Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.
摘要翻译：形成栅电极的方法可以通过在衬底中形成沟槽来形成，保形地形成多晶硅层，以在沟槽中形成多晶硅保形层，限定由多晶硅保形层围绕的凹槽，其中形成多晶硅保形层以延伸从衬底的表面向上并具有突起，并且突起具有邻近衬底表面的垂直外侧壁，在凹部中形成钨层以形成上表面，该上表面包括多晶硅保形层和钨之间的界面并且形成与多晶硅共形层和钨层的顶表面直接接触而没有任何中间层的覆盖层。

2. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

3. 发明授权

US07956464B2 Sputtering target and semiconductor device manufactured using the same 失效
标题翻译：溅射靶和使用其制造的半导体器件
公开(公告)号：US07956464B2
公开(公告)日：2011-06-07
申请号：US12573437
申请日：2009-10-05
申请人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
发明人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L23/532
CPC分类号： H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %.
摘要翻译：溅射靶包括钨（W） - 镍（Ni）合金，其中镍（Ni）的存在量为约0.01重量％至约1重量％。

4. 发明授权

US07875939B2 Semiconductor device including an ohmic layer 有权
标题翻译：包括欧姆层的半导体器件
公开(公告)号：US07875939B2
公开(公告)日：2011-01-25
申请号：US12453198
申请日：2009-05-01
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L23/532
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

5. 发明授权

US07772637B2 Semiconductor devices including gate structures and leakage barrier oxides 有权
标题翻译：包括栅极结构和漏电阻氧化物的半导体器件
公开(公告)号：US07772637B2
公开(公告)日：2010-08-10
申请号：US12401087
申请日：2009-03-10
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

6. 发明申请

US20100197101A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED METHOD 有权
标题翻译：半导体集成电路器件及相关方法
公开(公告)号：US20100197101A1
公开(公告)日：2010-08-05
申请号：US12754766
申请日：2010-04-06
申请人： Hee-sook PARK
发明人： Hee-sook PARK
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L29/66628
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第一层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

7. 发明申请

US20100120211A1 Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures 审中-公开
标题翻译：包括具有不同栅极结构的PMOS和NMOS晶体管的半导体器件的制造方法
公开(公告)号：US20100120211A1
公开(公告)日：2010-05-13
申请号：US12613746
申请日：2009-11-06
申请人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
发明人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/1052
摘要： A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed.
摘要翻译：半导体器件可以包括具有第一和第二区域的半导体衬底。半导体衬底的第一区域上的第一栅极结构可以包括在半导体衬底的第一区域上的金属氧化物电介质层和金属氧化物电介质层上的第一导电层。可以在第一栅极结构的相对侧的半导体衬底的第一区域中设置第一导电类型的第一和第二源极/漏极区域。半导体衬底的第二区域上的第二栅极结构可以包括基于氧化硅的电介质层和在氧化硅基介电层上的第二导电层。可以在第二栅极结构的相对侧的半导体衬底的第二区域中提供第二导电类型的第一和第二源极/漏极区域，其中第一和第二导电类型不同。还讨论了相关方法。

8. 发明申请

US20090298273A1 METHODS OF FORMING RECESSED GATE ELECTRODES HAVING COVERED LAYER INTERFACES 失效
标题翻译：形成具有覆盖层界面的顶盖电极的方法
公开(公告)号：US20090298273A1
公开(公告)日：2009-12-03
申请号：US12533672
申请日：2009-07-31
申请人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
发明人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L27/10876 , H01L21/28123 , H01L21/823437 , H01L27/10891 , H01L29/517 , H01L29/66621 , H01L29/7834
摘要： Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.
摘要翻译：形成栅电极的方法可以通过在衬底中形成沟槽来形成，保形地形成多晶硅层，以在沟槽中形成多晶硅保形层，限定由多晶硅保形层围绕的凹槽，其中形成多晶硅保形层以延伸从衬底的表面向上并具有突起，并且突起具有邻近衬底表面的垂直外侧壁，在凹部中形成钨层以形成上表面，该上表面包括多晶硅保形层和钨之间的界面并且形成与多晶硅保形层和钨层的顶表面直接接触而没有任何中间层的覆盖层。

9. 发明申请

US20090189229A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090189229A1
公开(公告)日：2009-07-30
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L21/283 , H01L23/532 , H01L29/78
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

10. 发明申请

US20090173986A1 Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides 有权
标题翻译：包括栅极结构和漏极氧化物的半导体器件
公开(公告)号：US20090173986A1
公开(公告)日：2009-07-09
申请号：US12401087
申请日：2009-03-10
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

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