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1. 发明申请

US20060110900A1 Method of forming a gate of a semiconductor device 有权
标题翻译：形成半导体器件的栅极的方法
公开(公告)号：US20060110900A1
公开(公告)日：2006-05-25
申请号：US11283121
申请日：2005-11-18
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28044 , H01L29/4925
摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.
摘要翻译：在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。因此，可能不会产生相邻布线之间的短路。

2. 发明授权

US07875939B2 Semiconductor device including an ohmic layer 有权
标题翻译：包括欧姆层的半导体器件
公开(公告)号：US07875939B2
公开(公告)日：2011-01-25
申请号：US12453198
申请日：2009-05-01
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L23/532
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

3. 发明授权

US07544597B2 Method of forming a semiconductor device including an ohmic layer 有权
标题翻译：形成包括欧姆层的半导体器件的方法
公开(公告)号：US07544597B2
公开(公告)日：2009-06-09
申请号：US11332476
申请日：2006-01-17
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

4. 发明授权

US07371669B2 Method of forming a gate of a semiconductor device 有权
标题翻译：形成半导体器件的栅极的方法
公开(公告)号：US07371669B2
公开(公告)日：2008-05-13
申请号：US11283121
申请日：2005-11-18
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/3205
CPC分类号： H01L21/28247 , H01L21/28044 , H01L29/4925
摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.
摘要翻译：在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。因此，可能不会产生相邻布线之间的短路。

5. 发明申请

US20060180875A1 Ohmic layer, semiconductor device including an ohmic layer, method of forming an ohmic layer and method of forming a semiconductor device including an ohmic layer 有权
标题翻译：欧姆层，包括欧姆层的半导体器件，形成欧姆层的方法和形成包括欧姆层的半导体器件的方法
公开(公告)号：US20060180875A1
公开(公告)日：2006-08-17
申请号：US11332476
申请日：2006-01-17
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

6. 发明授权

US07534709B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07534709B2
公开(公告)日：2009-05-19
申请号：US11233580
申请日：2005-09-23
申请人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
发明人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
IPC分类号： H01L21/3205
CPC分类号： H01L21/76841 , H01L21/28061 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L29/4933 , H01L29/4941
摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.
摘要翻译：本发明的实施例包括可以制造成具有较低电阻的半导体器件，以及形成半导体器件的方法。在多晶硅层和金属层之间形成电阻降低层。结果，多晶硅层和金属层之间的界面电阻大大降低，并且界面电阻的分布非常均匀。结果，包括电阻降低层的导电结构具有大大降低的薄层电阻以改善具有导电结构的半导体器件的电特性。

7. 发明申请

US20060014355A1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060014355A1
公开(公告)日：2006-01-19
申请号：US11233580
申请日：2005-09-23
申请人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
发明人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
IPC分类号： H01L21/20
CPC分类号： H01L21/76841 , H01L21/28061 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L29/4933 , H01L29/4941
摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.

8. 发明申请

US20080093660A1 Flash memory device and method for manufacturing the same 审中-公开
标题翻译：闪存装置及其制造方法
公开(公告)号：US20080093660A1
公开(公告)日：2008-04-24
申请号：US11653166
申请日：2007-01-12
申请人： Hee-Sook Park , Byung-Hak Lee , Tae-Ho Cha , Woong-Hee Sohn , Jang-Hee Lee , Jae-Hwa Park
发明人： Hee-Sook Park , Byung-Hak Lee , Tae-Ho Cha , Woong-Hee Sohn , Jang-Hee Lee , Jae-Hwa Park
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/40114 , H01L29/513
摘要： A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a second width smaller than the first width. The flash memory device further includes a sidewall spacer surrounding a side surface of the metal electrode to prevent oxidation of the metal electrode.
摘要翻译：闪速存储器件包括半导体衬底，栅极绝缘层，其具有形成在半导体衬底上的第一宽度，以捕获从半导体衬底隧穿的载流子，以及栅极绝缘层上的金属电极，以接收隧道所需的电压。金属电极的第二宽度小于第一宽度。闪存器件还包括围绕金属电极的侧表面的侧壁间隔件，以防止金属电极的氧化。

9. 发明授权

US07585787B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07585787B2
公开(公告)日：2009-09-08
申请号：US11648595
申请日：2007-01-03
申请人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
发明人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
IPC分类号： H01L21/469
CPC分类号： H01L29/4941 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11568 , H01L29/513
摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
摘要翻译：半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。第一电极和第二电极可以形成在电荷捕获结构上。可以在栅极结构上设置下电极和上电极。电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

10. 发明申请

US20080121983A1 Gate and method of forming the same, and memory device and method of manufacturing the same 审中-公开
标题翻译：门及其形成方法，以及存储器件及其制造方法
公开(公告)号：US20080121983A1
公开(公告)日：2008-05-29
申请号：US11606899
申请日：2006-12-01
申请人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
发明人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/40117 , H01L29/4234
摘要： A gate of a memory device may include a charge trapping structure having a tunnel oxide layer, a charge storing layer, and a blocking layer on a semiconductor substrate; a conductive pattern on the charge trapping structure, the conductive pattern including metal nitride; an ohmic film on the conductive pattern; and a gate electrode on the ohmic film.
摘要翻译：存储器件的栅极可以包括在半导体衬底上具有隧道氧化物层，电荷存储层和阻挡层的电荷俘获结构; 电荷捕获结构上的导电图案，导电图案包括金属氮化物; 导电图案上的欧姆膜; 和欧姆膜上的栅电极。

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