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1. 发明申请

US20100029073A1 Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers 失效
标题翻译：形成具有各向异性氧化氮化物层的集成电路器件的方法
公开(公告)号：US20100029073A1
公开(公告)日：2010-02-04
申请号：US12468296
申请日：2009-05-19
申请人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
发明人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
IPC分类号： H01L21/336 , H01L21/3105
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L21/3105 , H01L29/6653
摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.
摘要翻译：形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

2. 发明申请

US20090315091A1 GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE 有权
标题翻译：门结构和具有门结构的半导体器件
公开(公告)号：US20090315091A1
公开(公告)日：2009-12-24
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L29/49 , H01L27/10
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

3. 发明申请

US20120100708A1 Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers 审中-公开
标题翻译：形成具有各向异性氧化氮化物层的集成电路器件的方法
公开(公告)号：US20120100708A1
公开(公告)日：2012-04-26
申请号：US13176314
申请日：2011-07-05
申请人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
发明人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
IPC分类号： H01L21/28
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L21/3105 , H01L29/6653
摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.
摘要翻译：形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

4. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

5. 发明申请

US20090239368A1 Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same 审中-公开
标题翻译：形成氧化物层的方法和使用其形成浇口的方法
公开(公告)号：US20090239368A1
公开(公告)日：2009-09-24
申请号：US12408994
申请日：2009-03-23
申请人： Jae Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
发明人： Jae Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336 , H01L21/469 , H01L21/314
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/02238 , H01L21/02252 , H01L21/28247 , H01L21/31654 , H01L21/32105 , H01L29/40114 , H01L29/6659 , H01L29/7833
摘要： An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process.
摘要翻译：通过使用氢气和包括氧的气体的等离子体工艺在包括硅的层上选择性地形成氧化物层。通过向等离子体工艺中加入氦气，氢气被控制为具有小于总流量的约50％的流量。

6. 发明授权

US07989333B2 Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers 失效
标题翻译：形成具有各向异性氧化的氮化物层的集成电路器件的方法
公开(公告)号：US07989333B2
公开(公告)日：2011-08-02
申请号：US12468296
申请日：2009-05-19
申请人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
发明人： Jae-Hwa Park , Jong-Min Baek , Gil-Heyun Choi , Hee-Sook Park
IPC分类号： H01L21/3205
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L21/3105 , H01L29/6653
摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.
摘要翻译：形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

7. 发明申请

US20100120211A1 Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures 审中-公开
标题翻译：包括具有不同栅极结构的PMOS和NMOS晶体管的半导体器件的制造方法
公开(公告)号：US20100120211A1
公开(公告)日：2010-05-13
申请号：US12613746
申请日：2009-11-06
申请人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
发明人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/1052
摘要： A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed.
摘要翻译：半导体器件可以包括具有第一和第二区域的半导体衬底。半导体衬底的第一区域上的第一栅极结构可以包括在半导体衬底的第一区域上的金属氧化物电介质层和金属氧化物电介质层上的第一导电层。可以在第一栅极结构的相对侧的半导体衬底的第一区域中设置第一导电类型的第一和第二源极/漏极区域。半导体衬底的第二区域上的第二栅极结构可以包括基于氧化硅的电介质层和在氧化硅基介电层上的第二导电层。可以在第二栅极结构的相对侧的半导体衬底的第二区域中提供第二导电类型的第一和第二源极/漏极区域，其中第一和第二导电类型不同。还讨论了相关方法。

8. 发明授权

US07928498B2 Gate structures in semiconductor devices 有权
标题翻译：半导体器件中的栅极结构
公开(公告)号：US07928498B2
公开(公告)日：2011-04-19
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

9. 发明授权

US08404576B2 Methods of forming a gate structure 有权
标题翻译：形成栅极结构的方法
公开(公告)号：US08404576B2
公开(公告)日：2013-03-26
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/283
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散减少层图案，其上的非晶层图案扩散减少层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

10. 发明申请

US20090267132A1 GATE STRUCTURES IN SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的栅结构
公开(公告)号：US20090267132A1
公开(公告)日：2009-10-29
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788 , H01L29/78 , H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

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