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1. 发明授权

US07582931B2 Recessed gate electrodes having covered layer interfaces and methods of forming the same 失效
标题翻译：具有覆盖层界面的嵌入式栅电极及其形成方法
公开(公告)号：US07582931B2
公开(公告)日：2009-09-01
申请号：US11144142
申请日：2005-06-03
申请人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
发明人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
IPC分类号： H01L29/76
CPC分类号： H01L27/10876 , H01L21/28123 , H01L21/823437 , H01L27/10891 , H01L29/517 , H01L29/66621 , H01L29/7834
摘要： A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.
摘要翻译：晶体管的栅极可以包括在衬底中的沟槽中的多晶硅保形层和钨层之间的界面，以及覆盖沟槽并覆盖界面的覆盖层。还公开了相关方法。

2. 发明申请

US20060068535A1 Methods of fabricating semiconductor devices 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060068535A1
公开(公告)日：2006-03-30
申请号：US11216662
申请日：2005-08-31
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823481
摘要： Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen radical. The first oxidation process is carried out at a first temperature. A second oxidation process is carried out on the oxidized preliminary gate structure to provide a gate structure on the substrate, the second oxidation process being carried out at a second temperature, the second temperature being higher than the first temperature.
摘要翻译：提供了形成半导体器件的方法。在半导体衬底上形成初步栅极结构。预栅极结构包括栅极绝缘层图案，多晶硅层图案和导电层图案。使用氧自由基对预选栅极结构进行第一氧化处理。第一氧化过程在第一温度下进行。在氧化的预选栅极结构上进行第二氧化工艺以在衬底上提供栅极结构，第二氧化工艺在第二温度下进行，第二温度高于第一温度。

3. 发明申请

US20060057794A1 Semiconductor devices including high-k dielectric materials and methods of forming the same 失效
标题翻译：包括高k电介质材料的半导体器件及其形成方法
公开(公告)号：US20060057794A1
公开(公告)日：2006-03-16
申请号：US11227541
申请日：2005-09-15
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/8234
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.
摘要翻译：半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上包含掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层层，其包括在第二导电层上的金属。在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。控制栅极包括掺杂有P型杂质和金属层的多晶硅层。第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。还公开了方法实施例。

4. 发明申请

US20060051921A1 Methods of manufacturing semiconductor device gate structures by performing a surface treatment on a gate oxide layer 审中-公开
标题翻译：通过对栅极氧化物层进行表面处理来制造半导体器件栅极结构的方法
公开(公告)号：US20060051921A1
公开(公告)日：2006-03-09
申请号：US11215504
申请日：2005-08-30
申请人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jae-Hwa Park , Woong-Hee Sohn , Jong-Ryeol Yoo
发明人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jae-Hwa Park , Woong-Hee Sohn , Jong-Ryeol Yoo
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/28176 , H01L27/115 , H01L27/11521
摘要： In methods of manufacturing semiconductor devices, a preliminary gate oxide layer is formed on a substrate. A surface treatment process is performed on the preliminary gate oxide layer that reduces a diffusion of an oxidizing agent in the preliminary gate oxide layer to form a gate oxide layer on the substrate. A preliminary gate structure is formed on the gate oxide layer. The preliminary gate structure includes a first conductive layer pattern on the gate oxide layer and a second conductive layer pattern on the first conductive layer pattern. An oxidation process is performed on the preliminary gate structure using the oxidizing agent to form an oxide layer on a sidewall of the first conductive layer pattern and on the gate oxide layer, and to round at least one edge portion of the first conductive layer pattern.
摘要翻译：在半导体器件的制造方法中，在基板上形成预备栅氧化层。在预栅极氧化物层上进行表面处理工艺，其减少预选栅极氧化物层中的氧化剂的扩散，以在衬底上形成栅极氧化物层。在栅极氧化物层上形成初步栅极结构。预栅极结构包括栅极氧化物层上的第一导电层图案和第一导电层图案上的第二导电层图案。使用氧化剂对预选栅极结构进行氧化处理，以在第一导电层图案和栅极氧化物层的侧壁上形成氧化物层，并且使第一导电层图案的至少一个边缘部分圆弧化。

5. 发明申请

US20060081916A1 Methods of forming gate structures for semiconductor devices and related structures 有权
标题翻译：形成半导体器件和相关结构的栅极结构的方法
公开(公告)号：US20060081916A1
公开(公告)日：2006-04-20
申请号：US11221062
申请日：2005-09-07
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

6. 发明申请

US20050282338A1 Methods of forming gate patterns using isotropic etching of gate insulating layers 审中-公开
标题翻译：使用各向同性蚀刻栅极绝缘层形成栅极图案的方法
公开(公告)号：US20050282338A1
公开(公告)日：2005-12-22
申请号：US11153653
申请日：2005-06-15
申请人： Jong-Ryeol Yoo , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Sun-Pil Youn , Woong-Hee Sohn
发明人： Jong-Ryeol Yoo , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Sun-Pil Youn , Woong-Hee Sohn
IPC分类号： H01L21/28 , H01L21/302 , H01L21/336 , H01L21/461 , H01L21/4763 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28114 , H01L21/28061 , H01L21/28247 , H01L21/823462 , H01L29/42376 , H01L29/4941 , H01L29/517
摘要： A method for forming a gate pattern of a semiconductor device can include isotropically etching a gate insulating layer located between a gate conductive layer pattern and a substrate to recess an exposed side wall of the gate insulating layer pattern beyond a lower corner of the gate conductive layer pattern to form an undercut region. The gate conductive layer pattern can be treated to round off the lower corner.
摘要翻译：用于形成半导体器件的栅极图案的方法可以包括各向同性蚀刻位于栅极导电层图案和衬底之间的栅极绝缘层，以将栅极绝缘层图案的暴露的侧壁超出栅极导电层的下角形成底切区域。可以对栅极导电层图案进行处理以从下角四舍五入。

7. 发明申请

US20050272233A1 Recessed gate electrodes having covered layer interfaces and methods of forming the same 失效
标题翻译：具有覆盖层界面的嵌入式栅电极及其形成方法
公开(公告)号：US20050272233A1
公开(公告)日：2005-12-08
申请号：US11144142
申请日：2005-06-03
申请人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
发明人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/148 , H01L29/51 , H01L29/768 , H01L29/78
CPC分类号： H01L27/10876 , H01L21/28123 , H01L21/823437 , H01L27/10891 , H01L29/517 , H01L29/66621 , H01L29/7834
摘要： A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.
摘要翻译：晶体管的栅极可以包括在衬底中的沟槽中的多晶硅保形层和钨层之间的界面，以及覆盖沟槽并覆盖界面的覆盖层。还公开了相关方法。

8. 发明申请

US20060110900A1 Method of forming a gate of a semiconductor device 有权
标题翻译：形成半导体器件的栅极的方法
公开(公告)号：US20060110900A1
公开(公告)日：2006-05-25
申请号：US11283121
申请日：2005-11-18
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28044 , H01L29/4925
摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.
摘要翻译：在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。因此，可能不会产生相邻布线之间的短路。

9. 发明授权

US07696552B2 Semiconductor devices including high-k dielectric materials 失效
标题翻译：包括高k电介质材料的半导体器件
公开(公告)号：US07696552B2
公开(公告)日：2010-04-13
申请号：US11227541
申请日：2005-09-15
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.
摘要翻译：半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层层，其包括在第二导电层上的金属。在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。控制栅极包括掺杂有P型杂质和金属层的多晶硅层。第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。还公开了方法实施例。

10. 发明授权

US07521316B2 Methods of forming gate structures for semiconductor devices 有权
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07521316B2
公开(公告)日：2009-04-21
申请号：US11221062
申请日：2005-09-07
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

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