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1. 发明申请

US20060018143A1 Logical arrangement of memory arrays 有权
公开(公告)号：US20060018143A1
公开(公告)日：2006-01-26
申请号：US10896163
申请日：2004-07-21
申请人： Carl Taussig , Richard Elder , Hao Luo
发明人： Carl Taussig , Richard Elder , Hao Luo
IPC分类号： G11C5/02
CPC分类号： G11C5/063
摘要： An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.

2. 发明授权

US07817129B2 Integrated line selection apparatus within active matrix arrays 失效
标题翻译：有源矩阵阵列内集成选线装置
公开(公告)号：US07817129B2
公开(公告)日：2010-10-19
申请号：US11590339
申请日：2006-10-30
申请人： Warren Jackson , Carl Taussig , Hao Luo
发明人： Warren Jackson , Carl Taussig , Hao Luo
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3266 , G09G3/3275 , G09G3/3688 , G09G2300/0408 , G09G2310/0254 , G09G2310/0267 , G09G2310/0275 , G09G2310/0297 , G09G2320/043 , G09G2330/08
摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.
摘要翻译：描述了有源矩阵阵列内的集成线选择装置。该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极，通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

3. 发明申请

US20070096169A1 Structure and method for thin film device with stranded conductor 有权
标题翻译：具有绞线的薄膜器件的结构和方法
公开(公告)号：US20070096169A1
公开(公告)日：2007-05-03
申请号：US11264321
申请日：2005-11-01
申请人： Ping Mei , Hao Luo , Carl Taussig
发明人： Ping Mei , Hao Luo , Carl Taussig
IPC分类号： H01L29/80
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1218 , H01L29/78603
摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.
摘要翻译：本发明提供一种制造薄膜器件的薄膜器件和相关方法。例如，描述了逆变器薄膜器件的制造。此外，在基板上设置平行隔开的导电条。功能材料沉积在导电条上。然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。导电条的第一部分与TFD相邻捆扎。

4. 发明授权

US08318610B2 Method for thin film device with stranded conductor 有权
标题翻译：具有绞线的薄膜器件的方法
公开(公告)号：US08318610B2
公开(公告)日：2012-11-27
申请号：US13172543
申请日：2011-06-29
申请人： Ping Mei , Hao Luo , Carl Taussig
发明人： Ping Mei , Hao Luo , Carl Taussig
IPC分类号： H01L21/31
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1218 , H01L29/78603
摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.
摘要翻译：本发明提供一种制造薄膜器件的薄膜器件和相关方法。例如，描述了逆变器薄膜器件的制造。此外，在基板上设置平行隔开的导电条。功能材料沉积在导电条上。然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。导电条的第一部分与TFD相邻捆扎。

5. 发明申请

US20110256725A1 STRUCTURE AND METHOD FOR THIN FILM DEVICE WITH STRANDED CONDUCTOR 有权
标题翻译：具有带状导体的薄膜装置的结构和方法
公开(公告)号：US20110256725A1
公开(公告)日：2011-10-20
申请号：US13172543
申请日：2011-06-29
申请人： Ping Mei , Hao Luo , Carl Taussig
发明人： Ping Mei , Hao Luo , Carl Taussig
IPC分类号： H01L21/311
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1218 , H01L29/78603
摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.
摘要翻译：本发明提供一种制造薄膜器件的薄膜器件和相关方法。例如，描述了逆变器薄膜器件的制造。此外，在基板上设置平行隔开的导电条。功能材料沉积在导电条上。然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。导电条的第一部分与TFD相邻捆扎。

6. 发明授权

US07994509B2 Structure and method for thin film device with stranded conductor 有权
标题翻译：具有绞线的薄膜器件的结构和方法
公开(公告)号：US07994509B2
公开(公告)日：2011-08-09
申请号：US11264321
申请日：2005-11-01
申请人： Ping Mei , Hao Luo , Carl Taussig
发明人： Ping Mei , Hao Luo , Carl Taussig
IPC分类号： H01L29/10
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1218 , H01L29/78603
摘要： Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.
摘要翻译：本发明提供一种制造薄膜器件的薄膜器件和相关方法。例如，描述了逆变器薄膜器件的制造。此外，在基板上设置平行隔开的导电条。功能材料沉积在导电条上。然后在功能材料上提供3D结构，3D结构具有多个不同的高度，限定要捆扎的导电条的第一部分的至少一个高度。然后蚀刻3D结构和功能材料以限定设置在导电条的第一部分之上的TFD。导电条的第一部分与TFD相邻捆扎。

7. 发明授权

US06980465B2 Addressing circuit for a cross-point memory array including cross-point resistive elements 有权
标题翻译：用于包括交叉点电阻元件的交叉点存储器阵列的寻址电路
公开(公告)号：US06980465B2
公开(公告)日：2005-12-27
申请号：US10739350
申请日：2003-12-19
申请人： Carl Taussig , Warren Jackson , Hao Luo
发明人： Carl Taussig , Warren Jackson , Hao Luo
IPC分类号： G11C17/14 , G11C5/02 , G11C7/00 , G11C8/00 , G11C8/10 , G11C11/00 , G11C16/02 , G11C17/16 , G11C17/18 , H01L27/10
CPC分类号： G11C17/16 , G11C5/025 , G11C8/10 , G11C13/0023 , G11C17/165 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.
摘要翻译：寻址电路可操作以寻址交叉点存储器阵列中的一个或多个存储器元件。寻址电路包括用于寻址交叉点存储器阵列的第一组地址线和第二组地址线。地址电路还包括上拉和下拉电路元件。上拉和下拉电路元件和地址线都包括交叉点电阻元件。

8. 发明授权

US06567295B2 Addressing and sensing a cross-point diode memory array 有权
公开(公告)号：US06567295B2
公开(公告)日：2003-05-20
申请号：US09875496
申请日：2001-06-05
申请人： Carl Taussig , Richard Elder
发明人： Carl Taussig , Richard Elder
IPC分类号： G11C1706
CPC分类号： G11C8/10 , G11C17/06 , G11C17/18
摘要： A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The addressing circuit also has a second set of address lines with second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The first and second diode connections form a permuted diode logic circuit whereby application of predetermined voltages to selected subsets of the first and second address lines enables unique addressing of a single memory element in the array. By sensing the current in the address lines the binary state of the addressed memory element may be determined. Also, by application of a writing voltage to the selected subsets of address lines, the binary state of a memory element can be changed by substantially and permanently changing the resistance thereof.

9. 发明授权

US06552409B2 Techniques for addressing cross-point diode memory arrays 有权
标题翻译：用于寻址交叉点二极管存储器阵列的技术
公开(公告)号：US06552409B2
公开(公告)日：2003-04-22
申请号：US09875572
申请日：2001-06-05
申请人： Carl Taussig , Richard Elder
发明人： Carl Taussig , Richard Elder
IPC分类号： H01L2900
CPC分类号： B82Y10/00 , G11C8/10 , G11C17/16 , H01L23/5256 , H01L23/5382 , H01L25/105 , H01L2225/1023 , H01L2225/1064 , H01L2225/1082 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , Y10S257/91 , H01L2924/00
摘要： A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.
摘要翻译：存储器阵列及其一些寻址电路通过在由半导体材料层分隔的两层电极导体的交叉点处产生电路元件而形成。在交叉点处形成的电路元件用作存储器阵列中的数据存储设备，并且用作用于寻址阵列中的元件的置换寻址方案的连接。为了构造寻址电路，电极导体以选定的交叉点以受控的几何形状制造，使得所选择的电路元件具有增加或减少的横截面积。通过向电极施加编程电信号，可以根据受控电极几何形状来改变所选择的电路元件的电特性（例如电阻）。

10. 发明申请

US20050135146A1 Addressing circuit for a cross-point memory array including cross-point resistive elements 有权
公开(公告)号：US20050135146A1
公开(公告)日：2005-06-23
申请号：US10739350
申请日：2003-12-19
申请人： Carl Taussig , Warren Jackson , Hao Luo
发明人： Carl Taussig , Warren Jackson , Hao Luo
IPC分类号： G11C17/14 , G11C5/02 , G11C7/00 , G11C8/00 , G11C8/10 , G11C11/00 , G11C16/02 , G11C17/16 , G11C17/18 , H01L27/10
CPC分类号： G11C17/16 , G11C5/025 , G11C8/10 , G11C13/0023 , G11C17/165 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

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