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1. 发明授权

US5214650A Simultaneous voice and data system using the existing two-wire inter-face 失效
标题翻译：同步语音和数据系统采用现有的双线接口
公开(公告)号：US5214650A
公开(公告)日：1993-05-25
申请号：US615679
申请日：1990-11-19
申请人： Robert E. Renner , Kuang-Cheng Hu , Han Kem , John S. Young
发明人： Robert E. Renner , Kuang-Cheng Hu , Han Kem , John S. Young
IPC分类号： H04M11/06 , H04Q11/04
CPC分类号： H04M11/06 , H04Q11/0428 , H04Q2213/09 , H04Q2213/174 , H04Q2213/175 , H04Q2213/292 , H04Q2213/297 , H04Q2213/405 , Y10S370/914
摘要： A data adapter for simultaneously providing a low speed channel, a first high speed data channel, and a second high speed channel over a two wire connection; the two wire connection connects the data adapter to a telephone system. The data adapter includes a line transceiver connected to the two-wire connection, the line interface provides a full duplex transmission link with the telephone system over the two-wire connection. A telephone interface converts data between the first high speed channel and a telephone instrument. A rate adapter converts data between the second high speed channel and a data processing equipment. A protocol controller performs a packet protocol on the low speed channel, and routes the first high speed channel to the telephone interface and the second high speed channel to the rate adapter. A processor that receives and transmits messages through the protocol controller over the low speed channel to the telephone system, and in response to information received over the low speed channel, alternatively information received from the rate adapter, the processor controls the data adapter.
摘要翻译：一种数据适配器，用于同时提供低速通道，第一高速数据通道和通过双线连接的第二高速通道; 两线连接将数据适配器连接到电话系统。数据适配器包括连接到两线连接的线路收发器，线路接口通过双线连接提供与电话系统的全双工传输链路。电话接口在第一高速频道和电话乐器之间转换数据。速率适配器在第二高速通道和数据处理设备之间转换数据。协议控制器在低速信道上执行分组协议，并将第一高速信道路由到电话接口和第二高速信道到速率适配器。一种处理器，其通过协议控制器通过低速信道接收和发送消息到电话系统，并且响应于通过低速信道接收的信息，或者从速率适配器接收到的信息，处理器控制数据适配器。

2. 发明授权

US4991170A Circuit for interfacing a digital signal processor to a serial interface controller 失效
标题翻译：将数字信号处理器连接到串行接口控制器的电路
公开(公告)号：US4991170A
公开(公告)日：1991-02-05
申请号：US380370
申请日：1989-07-17
申请人： Han Kem
发明人： Han Kem
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： An interface circuit which connects a Digital-Signal-Processor (DSP) to a serial controller. The interface circuit includes a bi-directional multiplexer which converts the separate address and data busses of the DSP to the multiplexed data and address bus of the serial controller. A timing generator is included for keeping track of the number of clock cycles in the present access. A decoder connected to the timing generator decodes the number of clock cycles and generates the appropriate control signals to both the serial controller and the DSP.
摘要翻译：将数字信号处理器（DSP）连接到串行控制器的接口电路。接口电路包括双向多路复用器，其将DSP的单独地址和数据总线转换为串行控制器的复用数据和地址总线。包括定时发生器，用于跟踪当前访问中的时钟周期数。连接到定时发生器的解码器解码时钟周期数，并向串行控制器和DSP产生适当的控制信号。

3. 发明授权

US5023870A Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system 失效
标题翻译：接口电路，用于微处理器系统和时分复用系统之间的数据传输
公开(公告)号：US5023870A
公开(公告)日：1991-06-11
申请号：US369885
申请日：1989-06-22
申请人： Han Kem
发明人： Han Kem
IPC分类号： G06F13/376 , G06F13/42 , H04L29/06
CPC分类号： G06F13/376 , G06F13/4217 , H04L29/06
摘要： The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first synchronous system is a Time-Division-Multiplexing (TDM) system and the second synchronous system is a Microprocessor system. The transfer is allowed at the end of the assigned time slot provided that the microprocessor is not accessing the data. If the microprocessor is accessing the data, then the transfer is delayed for three clock cycles of the TDM clock. After the delay, if the microprocessor is still accessing the data, the transfer is delayed again. The delaying continues until the microprocessor is no longer accessing the data, at which time the transfer is allowed.
摘要翻译：本发明的电路提供了允许数据在第一同步系统与第二同步系统之间传输的信号。其中第一同步系统是时分多路复用（TDM）系统，第二同步系统是微处理器系统。如果微处理器没有访问数据，则在分配的时隙结束时允许转移。如果微处理器正在访问数据，则传输延迟TDM时钟的三个时钟周期。延迟后，如果微处理器仍在访问数据，传输将再次延迟。延迟持续到微处理器不再访问数据，此时允许传输。

4. 发明授权

US5058141A Single circuit for detecting a frame synchronization pattern and generating control signals 失效
标题翻译：用于检测帧同步模式和产生控制信号的单电路
公开(公告)号：US5058141A
公开(公告)日：1991-10-15
申请号：US486680
申请日：1990-03-01
申请人： Han Kem , John S. Young
发明人： Han Kem , John S. Young
IPC分类号： H04J3/06 , H04L7/04
CPC分类号： H04J3/0632 , H04L7/042
摘要： A single circuit for detecting a synchronization pattern in a serial data stream. Subsequent to detecting the synchronization pattern, the single circuit generates the control signals for converting the serial data to a parallel format and loading the parallel data into a first-in-first-out (FIFO) memory. The single circuit includes a controller arranged to receive the serial data stream. A counter is connected to the controller. When the counter is detecting the synchronization pattern and the synchronization pattern is being received, the counter is incremented. Absent the synchronization pattern being received, the counter is reset to a predetermined starting point. Subsequent to detecting the synchronization pattern, the counter generates a load signal. The single circuit further includes a pulse generator arranged to receive the load signal from the counter and generate a pulse of duration equal to a bit period of the serial data stream. An indicator is provided which generates an in-synch signal after the counter detects the synchronization pattern.
摘要翻译：用于检测串行数据流中的同步模式的单个电路。在检测到同步模式之后，单个电路产生用于将串行数据转换为并行格式并将并行数据加载到先进先出（FIFO）存储器中的控制信号。单个电路包括布置成接收串行数据流的控制器。计数器连接到控制器。当计数器检测到同步模式并且正在接收同步模式时，计数器递增。没有正在接收的同步模式，计数器被复位到预定的起始点。在检测到同步模式之后，计数器产生负载信号。单个电路还包括脉冲发生器，其布置成从计数器接收负载信号并产生等于串行数据流的位周期的持续时间的脉冲。提供指示器，其在计数器检测到同步模式之后产生同步信号。

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