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1. 发明授权

US08490107B2 Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels 有权
标题翻译：处理支持不同优先级的事务请求的集成电路中的资源分配
公开(公告)号：US08490107B2
公开(公告)日：2013-07-16
申请号：US13137362
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
IPC分类号： G06F9/46 , G06F15/16 , G06F15/173
CPC分类号： H04L47/821 , H04L47/70 , H04L47/805
摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.
摘要翻译：集成电路2包括经由基于环的互连30与共享高速缓存22,24进行通信的多个事务源6,8,10,12,14,16,18,20，每个具有相关联的POC / POS 30,34，以及作为请求维修电路。请求服务电路具有可被分配给不同事务的一组处理资源36。可以动态地或静态地分配这些处理资源。可以根据选择算法进行静态分配。该选择算法可以使用服务质量值/优先级作为其输入变量之一。还可以定义饥饿比例，使得如果饥饿分配太长时间，则强制选择较低的优先级。可以在服务质量值和优先级之间进行可编程映射。分配给每个优先级的处理资源的最大数量也可以被编程。

2. 发明申请

US20130042077A1 Data hazard handling for copending data access requests 有权
标题翻译：对待处理的数据访问请求的数据危害处理
公开(公告)号：US20130042077A1
公开(公告)日：2013-02-14
申请号：US13137356
申请日：2011-08-08
申请人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
发明人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F9/38 , G06F2212/621
摘要： A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. The data processing system process write requests in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data it responds to the first part and the data and state of the data prior to the write are sent as a second part of the write request. When there are copending reads and writes to the same address the writes are stalled by the coherency controller by not responding to the first part of the write and the initiator device proceeds to process any snoop requests received to the address of the write regardless of the fact that the write is pending. When the pending read has completed the coherency controller will respond to the first part of the write and the initiator device will complete the write by sending the data and an indicator of the state of the data following the snoop. The coherency controller can then avoid any potential data hazard using this information to update memory as required.
摘要翻译：公开了一种在一致性控制器而不是发起者设备处理数据危害的数据处理系统。数据处理系统以两部分的形式处理写入请求，使得发送第一部分，并且当一致性控制器具有接收对第一部分作出响应的数据的空间以及写入之前的数据和数据的状态发送时作为写请求的第二部分。当对相同地址进行共同读取和写入时，写入由相关性控制器停止，不响应写入的第一部分，并且启动器设备继续处理接收到写入地址的任何窥探请求，而不考虑事实写入待处理。当等待读取完成后，一致性控制器将响应写入的第一部分，发起者设备将通过发送数据和监听后的数据状态的指示符来完成写入。一致性控制器可以避免任何潜在的数据危害，使用此信息根据需要更新内存。

3. 发明授权

US07577727B2 Dynamic multiple cluster system reconfiguration 失效
标题翻译：动态多集群系统重构
公开(公告)号：US07577727B2
公开(公告)日：2009-08-18
申请号：US10607819
申请日：2003-06-27
申请人： Rajesh Kota , Shashank Newawarker , Guru Prasadh , Carl Zeitler , David B. Glasco
发明人： Rajesh Kota , Shashank Newawarker , Guru Prasadh , Carl Zeitler , David B. Glasco
IPC分类号： G06F15/177
CPC分类号： G06F15/17337
摘要： According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.
摘要翻译：根据本发明，提供了用于允许动态多集群系统配置改变的方法和装置。在一个示例中，多个集群系统中的处理器共享虚拟地址空间。提供了动态引入和删除处理器，I / O资源和集群的机制。这些机制可以在复位期间或系统运行时实现。链接可以动态启用或禁用。

4. 发明授权

US07395347B2 Communication between and within multi-processor clusters of multi-cluster computer systems 失效
标题翻译：在多集群计算机系统的多处理器集群之间和之间进行通信
公开(公告)号：US07395347B2
公开(公告)日：2008-07-01
申请号：US10635744
申请日：2003-08-05
申请人： Shashank Nemawarkar , Rajesh Kota , Guru Prasadh , Carl Zeitler , David B. Glasco
发明人： Shashank Nemawarkar , Rajesh Kota , Guru Prasadh , Carl Zeitler , David B. Glasco
IPC分类号： G06F15/16
CPC分类号： H04L1/0083 , H04L1/1664
摘要： Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received. The use of inter-cluster packets on an inter-cluster link is preferably transparent to other links and to the protocol layer.
摘要翻译：提供了改进的技术，用于检测和校正具有多个多处理器集群的计算机系统内的群间通信中的错误和偏差。每个群集的本地节点包括多个处理器和互连控制器。集群间链路在群集内的本地节点（包括互连控制器）之间形成。在不同集群的互连控制器之间形成集群间链路。群集内数据包可以串行化并封装成群集间数据包，用于在群集间链路上进行传输，最好采用链路层封装。每个群集间分组可以包括针对该分组计算的序列标识符和错误信息。时钟数据可以嵌入到在群集间链路的每个位通道上发送的符号中。可以存储发送的群集间分组的副本，直到接收到确认。在群集间链路上使用群集间分组优选地对于其他链路和协议层是透明的。

5. 发明授权

US07281055B2 Routing mechanisms in systems having multiple multi-processor clusters 失效
标题翻译：具有多个多处理器集群的系统中的路由机制
公开(公告)号：US07281055B2
公开(公告)日：2007-10-09
申请号：US10156893
申请日：2002-05-28
申请人： David Brian Glasco , Carl Zeitler , Rajesh Kota , Guru Prasadh , Richard R. Oehler
发明人： David Brian Glasco , Carl Zeitler , Rajesh Kota , Guru Prasadh , Richard R. Oehler
IPC分类号： G06F15/16 , G06F13/00
CPC分类号： G06F12/0284 , G06F15/17381
摘要： A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
摘要翻译：描述了一种多处理器计算机系统，其中提供地址映射，路由和事务识别机制，其使得能够互连多个多处理器集群，其中互连的处理器的数量超过有限的地址，节点标识和交易标签与每个单独的集群相关联的空间。

6. 发明授权

US5537629A Decoder for single cycle decoding of single prefixes in variable length instructions 失效
标题翻译：解码器，用于在可变长度指令中单个前缀的单周期解码
公开(公告)号：US5537629A
公开(公告)日：1996-07-16
申请号：US204593
申请日：1994-03-01
申请人： Gary L. Brown , Inderpreet S. Bhasin , R. Guru Prasadh
发明人： Gary L. Brown , Inderpreet S. Bhasin , R. Guru Prasadh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30149
摘要： A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.
摘要翻译：一种用于对可变长度指令码的多个前缀进行解码的前缀解码器，以便向多指令解码器提供多个前缀矢量，而不会造成一个时钟损失。并行前缀解码器包括多个前缀解码器，每个前缀解码器分别被耦合以从指令缓冲器接收指令字节，并响应于此提供包含编码前缀信息的前缀矢量，其格式为后续解码器逻辑易于使用。多路复用器接收多个前缀向量，并且如果转向宏指令具有单个前缀字节，则控制电路选择向宏指令解码器提供的前缀向量。如果多个宏指令被引导到多个宏指令解码器，则可以向每个解码器提供前缀向量。

7. 发明申请

US20150012713A1 DATA PROCESSING APPARATUS HAVING FIRST AND SECOND PROTOCOL DOMAINS, AND METHOD FOR THE DATA PROCESSING APPARATUS 有权
标题翻译：具有第一和第二协议域的数据处理装置，以及数据处理装置的方法
公开(公告)号：US20150012713A1
公开(公告)日：2015-01-08
申请号：US14380298
申请日：2012-03-02
申请人： William Henry Flanders , Ramamoorthy Guru Prasadh , Ashok Kumar Tummala , Jamshed Jalal , Phanindra Kumar Mannava
发明人： William Henry Flanders , Ramamoorthy Guru Prasadh , Ashok Kumar Tummala , Jamshed Jalal , Phanindra Kumar Mannava
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/60
摘要： A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B configured to operate under a snoop progress protocol. A deadlock condition is detected if a write target address for a pending write request issued from the first domain A to the second domain B is the same as a snoop target address or a pending snoop request issued from the second domain B to the first domain A. When the deadlock condition is detected, a bridge (4) between the domains may issue an early response to a selected one of the deadlocked write and snoop requests without waiting for the selected request serviced. The early response indicates to the domain that issued the selected request that the selected request has been serviced, enabling the other request to be serviced by the issuing domain.
摘要翻译：数据处理装置（2）包括被配置为在写入进程协议下操作的第一协议域A和被配置为在侦听进程协议下操作的第二协议域B. 如果从第一域A发送到第二域B的待决写入请求的写入目标地址与从第二域B向第一域A发出的窥探目标地址或未决侦听请求相同，则检测到死锁条件当检测到死锁状况时，域之间的桥（4）可以对所选择的一个死锁写和窥探请求发出早期响应，而不等待所服务的所选择的请求。早期响应向发出所选择的请求的域指示所选择的请求已经被服务，使得发出域能够服务其他请求。

8. 发明授权

US08463960B2 Synchronisation of data processing systems 有权
标题翻译：数据处理系统的同步
公开(公告)号：US08463960B2
公开(公告)日：2013-06-11
申请号：US13137358
申请日：2011-08-08
申请人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
发明人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F9/522
摘要： A centralised synchronizing device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system. A system synchronizing request is a request generated by one of the plurality of transaction generating devices and queries progress of a subset of the transaction requests. The synchronizing device includes: at least one port to and from the data processing system; a multicast circuitry configured to output a plurality of synchronizing requests for multicast to at least some of the devices within the data processing system where the requests query the progress of the subset of the transaction requests. Gather circuitry collects responses to the requests confirming that the queried progress has occurred at the respective devices. The gather circuitry determines when responses to all of the requests have been received and outputs a response to the system synchronizing request.
摘要翻译：一种用于确定通过数据处理系统发送的交易请求的至少一个子集的进度的集中同步装置。系统同步请求是由多个事务生成设备之一生成的请求，并查询事务请求子集的进度。所述同步装置包括：至少一个端口和从所述数据处理系统; 多路广播电路被配置为向所述数据处理系统内的至少一些设备输出多播同步请求，其中所述请求查询所述事务请求的子集的进度。收集电路收集对请求的响应，确认在相应设备上发生查询进度。收集电路确定何时接收到对所有请求的响应，并输出对系统同步请求的响应。

9. 发明申请

US20130042034A1 SYNCHRONISATION OF DATA PROCESSING SYSTEMS 有权
标题翻译：数据处理系统同步
公开(公告)号：US20130042034A1
公开(公告)日：2013-02-14
申请号：US13137358
申请日：2011-08-08
申请人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
发明人： Phanindra Kumar Mannava , Jamshed Jalal , Ramamoorthy Guru Prasadh , Michael Alan Filippo
IPC分类号： G06F3/00
CPC分类号： G06F9/522
摘要： A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests; the synchronising device comprising: at least one port for receiving requests from, and outputting requests and responses to, the data processing system; multicast circuitry configured to generate a plurality of synchronising requests in response to receipt of the system synchronising request and to output the plurality of synchronising requests for multicast to at least some of the devices within the data processing system, the synchronising requests querying the progress of the at least subset of the transaction requests at each of the respective devices; gather circuitry for collecting responses to the plurality of synchronising requests the responses confirming the queried progress has occurred at the respective device, the gather circuitry being configured to determine when responses to all of the plurality of synchronising requests have been received and in response to determining that all of the responses have been received to output a response to the system synchronising request.
摘要翻译：一种用于确定响应于系统同步请求的接收而通过数据处理系统发送的交易请求的至少一个子集的进度的集中同步装置，所述数据处理系统具有包括多个交易请求生成装置用于生成所述事务请求和用于接收所述事务请求的多个接收方设备，所述同步设备和用于互连所述设备中的至少一些的至少一个互连; 其中所述系统同步请求包括由所述多个交易产生装置之一生成的请求，并查询所述交易请求的所述至少一个子集的进度; 所述同步装置包括：至少一个端口，用于从所述数据处理系统接收请求并向所述数据处理系统输出请求和响应; 多播电路，被配置为响应于接收到所述系统同步请求而生成多个同步请求，并且将所述多个同步请求输出到所述数据处理系统内的至少一些设备，所述同步请求询问所述进程在每个相应设备的交易请求的至少子集; 收集用于收集对多个同步请求的响应的电路，确认所询问的进度的响应已经在相应的设备处发生，所述收集电路被配置为确定何时已经接收到对所有多个同步请求的所有响应，并响应于确定已收到所有响应以输出对系统同步请求的响应。

10. 发明授权

US07577755B2 Methods and apparatus for distributing system management signals 失效
标题翻译：分配系统管理信号的方法和装置
公开(公告)号：US07577755B2
公开(公告)日：2009-08-18
申请号：US10300408
申请日：2002-11-19
申请人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
发明人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
IPC分类号： G06F15/16 , G06F11/00
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
摘要翻译：提供了用于改善计算机系统综合体内的系统管理信号的分布的方法和装置。提供了在盒子内和计算机系统盒之间传输的机构。本地路由表和一般路由表允许将系统管理信号精确地分配给与特定分区相关联的资源。对信号进行排序，将与一个或多个框相关联的资源置于适当的状态。可以在不使用专用线的情况下实现计算机系统复合体中的盒之间的信号分配。

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