发明申请
US20090311846A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS
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基本信息:
- 专利标题： METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS
- 专利标题（中）：在具有NMOS和PMOS区域的器件中形成低温分离区的方法
- 申请号：US12466178 申请日：2009-05-14
- 公开(公告)号：US20090311846A1 公开(公告)日：2009-12-17
- 发明人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
- 申请人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 优先权： KR10-2008-0054860 20080611
- 主分类号： H01L21/762
- IPC分类号： H01L21/762
摘要：
A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要（中）：
在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。 在单元区域，PMOS区域和NMOS区域中形成沟槽。 在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。 在衬底上形成第一器件隔离绝缘层，填充沟槽。 去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。 衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。 在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。 去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。
公开/授权文献:
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/67 | .专门适用于在制造或处理过程中处理半导体或电固体器件的装置；专门适合于在半导体或电固体器件或部件的制造或处理过程中处理晶片的装置 |
| ----------H01L21/71 | ..限定在组H01L21/70中的器件的特殊部件的制造 |
| ------------H01L21/76 | ...组件间隔离区的制作 |
| --------------H01L21/762 | ....介电区 |