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1. 发明申请

US20130060556A1 SYSTEMS AND METHODS OF RUNTIME SYSTEM FUNCTION ACCELERATION FOR CMP DESIGN 审中-公开
标题翻译：用于CMP设计的运行系统功能加速系统和方法
公开(公告)号：US20130060556A1
公开(公告)日：2013-03-07
申请号：US13548805
申请日：2012-07-13
申请人： Guang R. GAO
发明人： Guang R. GAO
IPC分类号： G06G7/62
CPC分类号： G06F17/5045
摘要： A chip-level multiprocessing system may be designed for accelerated implementation of a specified user computing application. The application may be converted to a parallel program representation with explicit runtime functions denoted. One or more of the explicit runtime functions may be identified for implementation in the form of a specialized intellectual property core (IP-core). The remaining portions of the application may then be implemented in a further IP-core, and the IP-cores may be interconnected to implement the user computing application.
摘要翻译：芯片级多处理系统可以被设计用于加速实现指定的用户计算应用。应用程序可以转换为具有显式运行时功能的并行程序表示。可以以专门的知识产权核心（IP核）的形式来识别一个或多个显式运行时功能以实现。应用的剩余部分然后可以在另一IP核中实现，并且IP核可以互连以实现用户计算应用。

2. 发明授权

US07356454B2 Method and apparatus for emulation of logic circuits 失效
标题翻译：用于仿真逻辑电路的方法和装置
公开(公告)号：US07356454B2
公开(公告)日：2008-04-08
申请号：US10967814
申请日：2004-10-18
申请人： Hirofumi Sakane , Levent Yakay , Vishal Karna , Clement Leung , Guang R. Gao
发明人： Hirofumi Sakane , Levent Yakay , Vishal Karna , Clement Leung , Guang R. Gao
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.
摘要翻译：公开了一种用于模拟具有至少一组相同的逻辑模块的逻辑电路的方法。集合中的每个逻辑模块具有存储该逻辑模块的模块状态的逻辑元件和存储器元件。通过从一组相同的逻辑模块提取逻辑模块来仿真逻辑电路，用逻辑元件的单个实例翻译所提取的逻辑模块以用于每个逻辑模块的模块状态的迭代表示，以及配置逻辑器件用翻译的逻辑模块来仿真逻辑电路。

3. 发明授权

US09542231B2 Efficient execution of parallel computer programs 有权
标题翻译：并行计算机程序的有效执行
公开(公告)号：US09542231B2
公开(公告)日：2017-01-10
申请号：US13086132
申请日：2011-04-13
申请人： Rishi L. Khan , Daniel Orozco , Guang R. Gao
发明人： Rishi L. Khan , Daniel Orozco , Guang R. Gao
IPC分类号： G06F9/46 , G06F9/50 , G06F9/45
CPC分类号： G06F9/5066 , G06F8/451 , G06F9/5094 , G06F2209/501 , Y02D10/22 , Y02D10/36
摘要： The present invention, known as runspace, relates to the field of computing system management, data processing and data communications, and specifically to synergistic methods and systems which provide resource-efficient computation, especially for decomposable many-component tasks executable on multiple processing elements, by using a metric space representation of code and data locality to direct allocation and migration of code and data, by performing analysis to mark code areas that provide opportunities for runtime improvement, and by providing a low-power, local, secure memory management system suitable for distributed invocation of compact sections of code accessing local memory. Runspace provides mechanisms supporting hierarchical allocation, optimization, monitoring and control, and supporting resilient, energy efficient large-scale computing.
摘要翻译：称为运行空间的本发明涉及计算系统管理，数据处理和数据通信领域，特别涉及提供资源有效计算的协同方法和系统，特别是对于可执行于多个处理单元的可分解多组件任务，通过使用代码和数据位置的度量空间表示来直接分配和迁移代码和数据，通过执行分析来标记为运行时改进提供机会的代码区域，以及提供适合于运行时的低功耗，本地，安全的存储器管理系统用于分布式调用访问本地内存的代码的紧凑部分。 Runspace提供支持分层分配，优化，监控和控制的机制，并支持弹性，高能效的大规模计算。

4. 发明授权

US08341568B2 Systems and methods for logic verification 有权
标题翻译：用于逻辑验证的系统和方法
公开(公告)号：US08341568B2
公开(公告)日：2012-12-25
申请号：US12840543
申请日：2010-07-21
申请人： Fei Chen , Guang R. Gao
发明人： Fei Chen , Guang R. Gao
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.
摘要翻译：用于模拟逻辑的方法和系统可以将逻辑设计转换为用于基于多处理器的并行逻辑仿真设备的可执行代码。系统可以实现一个或多个并行执行方法，其可以包括IPMD，MPMD和/或DDMT。

5. 发明申请

US20100286976A1 Systems and Methods for Logic Verification 有权
标题翻译：逻辑验证系统与方法
公开(公告)号：US20100286976A1
公开(公告)日：2010-11-11
申请号：US12840543
申请日：2010-07-21
申请人： Guang R. Gao , Fei Chen
发明人： Guang R. Gao , Fei Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.
摘要翻译：用于模拟逻辑的方法和系统可以将逻辑设计转换为用于基于多处理器的并行逻辑仿真设备的可执行代码。系统可以实现一个或多个并行执行方法，其可以包括IPMD，MPMD和/或DDMT。

6. 发明授权

US07631305B2 Methods and products for processing loop nests 失效
标题翻译：加工环巢的方法和产品
公开(公告)号：US07631305B2
公开(公告)日：2009-12-08
申请号：US10944986
申请日：2004-09-20
申请人： Hongbo Rong , Guang R. Gao , Alban Douillet , Ramaswamy Govindarajan
发明人： Hongbo Rong , Guang R. Gao , Alban Douillet , Ramaswamy Govindarajan
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F9/3013 , G06F9/30134 , G06F9/325
摘要： Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing iterations of the outermost loop, running the software kernel and rotating a register file for each stage of the software kernel preceding an innermost loop to generate code to prepare for filling and executing instructions in software pipelines for a current group, running the software kernel for each stage of the software kernel in the innermost loop to generate code to fill the software pipelines for the current group with the register file being rotated after at least one run of the software kernel for the innermost loop, and repeatedly running the software kernel to unroll inner loops to generate code to further fill the software pipelines for the current group.
摘要翻译：公开了用于处理指令的软件内核的方法和产品。软件内核具有代表循环嵌套的阶段。软件内核通过将最外层循环的迭代划分成组，每组代表最外层循环的迭代，运行软件内核并旋转位于最内圈之前的软件内核的每个阶段的寄存器文件来生成代码以准备在当前组的软件管道中填充和执行指令，为最内层循环中的软件内核的每个阶段运行软件内核，以生成代码以填充当前组的软件流水线，其中寄存器文件在至少一次运行后旋转的软件内核，并重复运行软件内核以展开内部循环以生成代码，以进一步填充当前组的软件流水线。

7. 发明申请

US20090222252A1 DATA DRIVEN LOGIC SIMULATION CHIP AND TOOLCHAIN 有权
标题翻译：数据驱动逻辑模拟芯片和工具
公开(公告)号：US20090222252A1
公开(公告)日：2009-09-03
申请号：US12392666
申请日：2009-02-25
申请人： Fei Chen , Guang R. Gao
发明人： Fei Chen , Guang R. Gao
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.
摘要翻译：可以使用装置和方法将硬件逻辑设计编译成在数据驱动芯片上执行的数据驱动逻辑程序。该装置可以包括具有用于定义由综合工具合成的网络列表的库的存储。该装置还可以包括包括多个逻辑处理器的数据驱动逻辑验证芯片。该装置还可以包括代码发生器，用于采用启发式方法将网络列表转换为数据驱动的逻辑程序，并用于分配硬件资源以平衡跨越验证芯片的多个逻辑处理器的计算和存储负载。

8. 发明申请

US20110289507A1 RUNSPACE METHOD, SYSTEM AND APPARATUS 有权
标题翻译： RUNSPACE方法，系统和设备
公开(公告)号：US20110289507A1
公开(公告)日：2011-11-24
申请号：US13086132
申请日：2011-04-13
申请人： Rishi L. Khan , Daniel Orozco , Guang R. Gao
发明人： Rishi L. Khan , Daniel Orozco , Guang R. Gao
IPC分类号： G06F9/46
CPC分类号： G06F9/5066 , G06F8/451 , G06F9/5094 , G06F2209/501 , Y02D10/22 , Y02D10/36
摘要： The present invention, known as runspace, relates to the field of computing system management, data processing and data communications, and specifically to synergistic methods and systems which provide resource-efficient computation, especially for decomposable many-component tasks executable on multiple processing elements, by using a metric space representation of code and data locality to direct allocation and migration of code and data, by performing analysis to mark code areas that provide opportunities for runtime improvement, and by providing a low-power, local, secure memory management system suitable for distributed invocation of compact sections of code accessing local memory. Runspace provides mechanisms supporting hierarchical allocation, optimization, monitoring and control, and supporting resilient, energy efficient large-scale computing.
摘要翻译：称为运行空间的本发明涉及计算系统管理，数据处理和数据通信领域，特别涉及提供资源有效计算的协同方法和系统，特别是对于可执行于多个处理单元的可分解多组件任务，通过使用代码和数据位置的度量空间表示来直接分配和迁移代码和数据，通过执行分析来标记为运行时改进提供机会的代码区域，以及提供适合于运行时的低功耗，本地，安全的存储器管理系统用于分布式调用访问本地内存的代码的紧凑部分。 Runspace提供支持分层分配，优化，监控和控制的机制，并支持弹性，高能效的大规模计算。

9. 发明申请

US20110246823A1 TASK-ORIENTED NODE-CENTRIC CHECKPOINTING (TONCC) 审中-公开
标题翻译：以任务为中心的中心检查点（TONCC）
公开(公告)号：US20110246823A1
公开(公告)日：2011-10-06
申请号：US13080590
申请日：2011-04-05
申请人： Rishi L. Khan , Guang R. Gao , Apperson H. Johnson
发明人： Rishi L. Khan , Guang R. Gao , Apperson H. Johnson
IPC分类号： G06F11/07
CPC分类号： G06F11/1438
摘要： Node-centric checkpointing may be used in a multi-node computing system to provide fault-tolerance. Such checkpointing may involve storage of input and/or output data prior to and/or after execution of a task on a node.
摘要翻译：以节点为中心的检查点可用于多节点计算系统中以提供容错能力。这种检查点可以涉及在节点上的任务执行之前和/或之后存储输入和/或输出数据。

10. 发明申请

US20080294411A1 Systems and Methods for Logic Verification 有权
标题翻译：逻辑验证系统与方法
公开(公告)号：US20080294411A1
公开(公告)日：2008-11-27
申请号：US11937577
申请日：2007-11-09
申请人： Guang R. Gao , Fei Chen
发明人： Guang R. Gao , Fei Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.
摘要翻译：用于模拟逻辑的方法和系统可以将逻辑设计转换为用于基于多处理器的并行逻辑仿真设备的可执行代码。系统可以实现一个或多个并行执行方法，其可以包括IPMD，MPMD和/或DDMT。

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