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    • 1. 发明授权
    • Data driven logic simulation
    • 数据驱动逻辑模拟
    • US08365111B2
    • 2013-01-29
    • US12392666
    • 2009-02-25
    • Fei ChenGuang R. Gao
    • Fei ChenGuang R. Gao
    • G06F17/50G06G7/62
    • G06F17/5022
    • An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.
    • 可以使用装置和方法将硬件逻辑设计编译成在数据驱动芯片上执行的数据驱动逻辑程序。 该装置可以包括具有用于定义由综合工具合成的网络列表的库的存储。 该装置还可以包括包括多个逻辑处理器的数据驱动逻辑验证芯片。 该装置还可以包括代码发生器,用于采用启发式方法将网络列表转换为数据驱动的逻辑程序,并用于分配硬件资源以平衡跨越验证芯片的多个逻辑处理器的计算和存储负载。
    • 5. 发明申请
    • DATA DRIVEN LOGIC SIMULATION CHIP AND TOOLCHAIN
    • 数据驱动逻辑模拟芯片和工具
    • US20090222252A1
    • 2009-09-03
    • US12392666
    • 2009-02-25
    • Fei ChenGuang R. Gao
    • Fei ChenGuang R. Gao
    • G06F17/50
    • G06F17/5022
    • An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.
    • 可以使用装置和方法将硬件逻辑设计编译成在数据驱动芯片上执行的数据驱动逻辑程序。 该装置可以包括具有用于定义由综合工具合成的网络列表的库的存储。 该装置还可以包括包括多个逻辑处理器的数据驱动逻辑验证芯片。 该装置还可以包括代码发生器,用于采用启发式方法将网络列表转换为数据驱动的逻辑程序,并用于分配硬件资源以平衡跨越验证芯片的多个逻辑处理器的计算和存储负载。
    • 10. 发明申请
    • Reagents for reversibly terminating primer extension
    • 可逆终止引物延伸的试剂
    • US20110275124A1
    • 2011-11-10
    • US12383306
    • 2009-03-23
    • Steven A. BennerDaniel HutterNicole Aurora LealFei Chen
    • Steven A. BennerDaniel HutterNicole Aurora LealFei Chen
    • C12P19/34C07H19/14C07H19/20C07H19/10C07H19/073
    • C07H19/10C07H19/073C07H19/14C07H19/173C07H23/00
    • This invention relates to the field of nucleic acid chemistry, more specifically to the field of compositions of matter that comprise triphosphates of modified 2′-deoxynucleosides and oligonucleotides that are formed when these are appended to the 3′-end of a primer, wherein said modifications comprise NH2 moiety attached to their 3′-hydroxyl group and a fluorescent species in a form of a tag affixed to the nucleobase via a linker that can be cleaved. Such compositions and their associated processes enable and improve the sequencing of oligonucleotides using a strategy of cyclic reversible termination, as outlined in U.S. Pat. No. 6,664,079. Most specifically, the invention concerns compositions of matter that are 5′-triphosphates of ribo- and 2′-deoxyribonucleosides carrying detectable tags and oligonucleotides that might be derived from them. The invention also concerns processes wherein a DNA polymerase, RNA polymerase, or reverse transcriptase synthesizes said oligonucleotides via addition of said triphosphates to a primer.
    • 本发明涉及核酸化学领域,更具体地涉及包含修饰的2'-脱氧核苷的三磷酸的物质组合物领域和当它们附着在引物的3'-末端时形成的寡核苷酸,其中所述 修饰包括连接到它们的3'-羟基上的NH 2部分和通过能够被切割的接头固定在核碱基上的标签形式的荧光物质。 这样的组合物及其相关方法使用循环可逆终止的策略实现和改进了寡核苷酸的测序,如美国专利No. 6,664,079。 最具体地,本发明涉及携带检测标签的核糖核酸和2'-脱氧核糖核苷的5'-三磷酸的物质组合物,所述可检测标签和寡核苷酸可能来源于它们。 本发明还涉及其中DNA聚合酶,RNA聚合酶或逆转录酶通过向引物中加入所述三磷酸合成所述寡核苷酸的方法。