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1. 发明授权

US07631305B2 Methods and products for processing loop nests 失效
标题翻译：加工环巢的方法和产品
公开(公告)号：US07631305B2
公开(公告)日：2009-12-08
申请号：US10944986
申请日：2004-09-20
申请人： Hongbo Rong , Guang R. Gao , Alban Douillet , Ramaswamy Govindarajan
发明人： Hongbo Rong , Guang R. Gao , Alban Douillet , Ramaswamy Govindarajan
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F9/3013 , G06F9/30134 , G06F9/325
摘要： Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing iterations of the outermost loop, running the software kernel and rotating a register file for each stage of the software kernel preceding an innermost loop to generate code to prepare for filling and executing instructions in software pipelines for a current group, running the software kernel for each stage of the software kernel in the innermost loop to generate code to fill the software pipelines for the current group with the register file being rotated after at least one run of the software kernel for the innermost loop, and repeatedly running the software kernel to unroll inner loops to generate code to further fill the software pipelines for the current group.
摘要翻译：公开了用于处理指令的软件内核的方法和产品。软件内核具有代表循环嵌套的阶段。软件内核通过将最外层循环的迭代划分成组，每组代表最外层循环的迭代，运行软件内核并旋转位于最内圈之前的软件内核的每个阶段的寄存器文件来生成代码以准备在当前组的软件管道中填充和执行指令，为最内层循环中的软件内核的每个阶段运行软件内核，以生成代码以填充当前组的软件流水线，其中寄存器文件在至少一次运行后旋转的软件内核，并重复运行软件内核以展开内部循环以生成代码，以进一步填充当前组的软件流水线。

2. 发明申请

US20050097509A1 Methods and products for processing loop nests 失效
标题翻译：加工环巢的方法和产品
公开(公告)号：US20050097509A1
公开(公告)日：2005-05-05
申请号：US10944986
申请日：2004-09-20
申请人： Hongbo Rong , Guang Gao , Alban Douillet , Ramaswamy Govindarajan
发明人： Hongbo Rong , Guang Gao , Alban Douillet , Ramaswamy Govindarajan
IPC分类号： G06F9/30 , G06F9/32 , G06F9/44 , G06F9/45
CPC分类号： G06F8/4452 , G06F9/3013 , G06F9/30134 , G06F9/325
摘要： Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing iterations of the outermost loop, running the software kernel and rotating a register file for each stage of the software kernel preceding an innermost loop to generate code to prepare for filling and executing instructions in software pipelines for a current group, running the software kernel for each stage of the software kernel in the innermost loop to generate code to fill the software pipelines for the current group with the register file being rotated after at least one run of the software kernel for the innermost loop, and repeatedly running the software kernel to unroll inner loops to generate code to further fill the software pipelines for the current group.
摘要翻译：公开了用于处理指令的软件内核的方法和产品。软件内核具有代表循环嵌套的阶段。软件内核通过将最外层循环的迭代划分成组，每组代表最外层循环的迭代，运行软件内核并旋转位于最内圈之前的软件内核的每个阶段的寄存器文件来生成代码以准备在当前组的软件管道中填充和执行指令，为最内层循环中的软件内核的每个阶段运行软件内核，以生成代码以填充当前组的软件流水线，其中寄存器文件在至少一次运行后旋转的软件内核，并重复运行软件内核以展开内部循环以生成代码，以进一步填充当前组的软件流水线。

3. 发明申请

US20140298306A1 SOFTWARE PIPELINING AT RUNTIME 有权
标题翻译：软件管道运行
公开(公告)号：US20140298306A1
公开(公告)日：2014-10-02
申请号：US13853430
申请日：2013-03-29
申请人： Hongbo Rong , Hyunchul Park , Youfeng Wu
发明人： Hongbo Rong , Hyunchul Park , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.
摘要翻译：设备和方法可以提供用于通过动态编译器来确定用于处理一个或多个循环的性能水平，并且执行代码优化以生成用于在规定时间段内实现所确定的性能水平的所述一个或多个循环的流水线调度。在一个示例中，可以为一个或多个循环建立依赖图，并且可以基于性能水平将每个依赖图划分成多个阶段。

4. 发明申请

US20180004496A1 TECHNOLOGIES FOR OPTIMIZING SPARSE MATRIX CODE WITH FIELD-PROGRAMMABLE GATE ARRAYS 有权
公开(公告)号：US20180004496A1
公开(公告)日：2018-01-04
申请号：US15200053
申请日：2016-07-01
申请人： Hongbo Rong , Gilles A. Pokam
发明人： Hongbo Rong , Gilles A. Pokam
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/447 , G06F8/452 , G06F9/45525
摘要： Technologies for optimizing sparse matrix code include a target computing device having a processor and a field-programmable gate array (FPGA). A compiler identifies a performance-critical loop in a sparse matrix source code and generates optimized executable code, including processor code and FPGA code. The target computing device executes the optimized executable code, using the processor for the processor code and the FPGA for the FPGA code. The processor executes a first iteration of the loop, generates reusable optimization data in response to executing the first iteration, and stores the reusable optimization data in a shared memory. The FPGA accesses the optimization data in the shared memory, executes additional iterations of the loop, and optimizes the additional iterations of the loop based on the optimization data. The optimization data may include, for example, loop-invariant data, reordered data, or alternate data storage representations. Other embodiments are described and claimed.

5. 发明授权

US09715388B2 Instruction and logic to monitor loop trip count and remove loop optimizations 有权
公开(公告)号：US09715388B2
公开(公告)日：2017-07-25
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/32 , G06F9/30 , G06F9/38 , G06F11/34 , G06F9/45
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to monitor loop trip count are disclosed. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.

6. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

7. 发明申请

US20140208085A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：US20140208085A1
公开(公告)日：2014-07-24
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

8. 发明申请

US20150212836A1 CONJUGATE CODE GENERATION FOR EFFICIENT DYNAMIC OPTIMIZATIONS 审中-公开
标题翻译：有效动态优化的合并代码生成
公开(公告)号：US20150212836A1
公开(公告)日：2015-07-30
申请号：US14126894
申请日：2013-10-24
申请人： Hongbo Rong , Hyunchul Park , Cheng Wang , Youfeng Wu
发明人： Hongbo Rong , Hyunchul Park , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/4552 , G06F8/4442 , G06F8/52 , G06F9/45508 , G06F9/45533
摘要： Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.
摘要翻译：描述了用于有效动态优化的共轭码生成相关的方法和装置。在一个实施例中，至少部分地基于源程序生成二进制代码和中间表示（IR）代码。二进制代码和中间代码被传送到虚拟机逻辑。二进制代码和IR代码每个包括一对一对应的多个区域。还要求保护和描述其它实施例。

9. 发明申请

US20150169226A1 TECHNOLOGIES FOR PERSISTENT MEMORY PROGRAMMING 有权
标题翻译：不间断内存编程技术
公开(公告)号：US20150169226A1
公开(公告)日：2015-06-18
申请号：US14496621
申请日：2014-09-25
申请人： Xipeng Shen , Youfeng Wu , Cheng Wang , Hyunchul Park , Hongbo Rong
发明人： Xipeng Shen , Youfeng Wu , Cheng Wang , Hyunchul Park , Hongbo Rong
IPC分类号： G06F3/06
CPC分类号： G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
摘要： Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.
摘要翻译：用于持久存储器编程的技术包括具有包括一个或多个非易失性区域的持久存储器的计算设备。计算设备可以使用持久指针策略将永久存储器中的目标位置的虚拟存储器地址分配给持久存储器指针，并且可以使用相同的策略来解除引用。持续指标策略包括持有人，价值观，乐观整改和悲观整改。在执行数据一致性部分期间，计算设备可以将改变记录到持久存储器，并且当最后数据一致性部分结束时，向永久存储器提交更改。数据一致性部分可以按日志组标识符分组。使用存储在非易失性区域中的类型元数据，计算设备可以识别非易失性区域内的根对象的类型，然后递归地标识由根对象引用的所有对象的类型。描述和要求保护其他实施例。

10. 发明申请

US20170147301A1 TECHNOLOGIES FOR AUTOMATIC REORDERING OF SPARSE MATRICES 审中-公开
公开(公告)号：US20170147301A1
公开(公告)日：2017-05-25
申请号：US14946200
申请日：2015-11-19
申请人： Hongbo Rong , Jongsoo Park , Todd A. Anderson
发明人： Hongbo Rong , Jongsoo Park , Todd A. Anderson
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/4434 , G06F8/4442 , G06F17/16
摘要： Technologies for automatic reordering of sparse matrices include a computing device to determine a distributivity of an expression defined in a code region of a program code. The expression is determined to be distributive if semantics of the expression are unaffected by a reordering of an input/output of the expression. The computing device performs inter-dependent array analysis on the expression to determine one or more clusters of inter-dependent arrays of the expression, wherein each array of a cluster of the one or more clusters is inter-dependent on each other array of the cluster, and performs bi-directional data flow analysis on the code region by iterative backward and forward propagation of reorderable arrays through expressions in the code region based on the one or more clusters of the inter-dependent arrays. The backward propagation is based on a backward transfer function and the forward propagation is based on a forward transfer function.

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