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1. 发明申请

US20110154116A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
公开(公告)号：US20110154116A1
公开(公告)日：2011-06-23
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F11/07
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

2. 发明授权

US08521992B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
标题翻译：在无序微处理器中预测和避免操作与存储比较的危害
公开(公告)号：US08521992B2
公开(公告)日：2013-08-27
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

3. 发明申请

US20110153986A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
标题翻译：预期和避免操作不合格的微处理器中的操作和比较危害
公开(公告)号：US20110153986A1
公开(公告)日：2011-06-23
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

4. 发明授权

US08468325B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

5. 发明授权

US09135005B2 History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties 有权
标题翻译：用于存储用于优化操作数存储的多个指令的基于历史和对齐的破解比较处罚
公开(公告)号：US09135005B2
公开(公告)日：2015-09-15
申请号：US12695687
申请日：2010-01-28
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

6. 发明授权

US09223687B2 Determining the logical address of a transaction abort 有权
标题翻译：确定事务中止的逻辑地址
公开(公告)号：US09223687B2
公开(公告)日：2015-12-29
申请号：US13524342
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/02 , G06F12/00 , G06F12/08 , G06F9/30 , G06F9/38
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.
摘要翻译：实施例涉及确定事务中止的逻辑地址。在一个实施例中，从应用程序接收一个或多个接收的指令。一个或多个指令在第一事务中执行。第一个交易延迟将存储提交到内存，直到它完成。所述一个或多个指令中的至少一个包括第一逻辑存储器地址。第一逻辑存储器地址对应于存储器系统中的第一存储器地址。确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。

7. 发明授权

US09152566B2 Prefetch address translation using prefetch buffer based on availability of address translation logic 有权
标题翻译：基于地址转换逻辑的可用性，使用预取缓冲区预取地址转换
公开(公告)号：US09152566B2
公开(公告)日：2015-10-06
申请号：US13523919
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F12/1009
摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
摘要翻译：实施例涉及计算机处理器中的预取地址转换。一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。

8. 发明申请

US20140082252A1 Combined Two-Level Cache Directory 审中-公开
标题翻译：组合二级缓存目录
公开(公告)号：US20140082252A1
公开(公告)日：2014-03-20
申请号：US13621465
申请日：2012-09-17
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0811 , G06F12/1054
摘要： Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal.
摘要翻译：响应于接收高速缓存访问的逻辑地址，机制在本地高速缓存目录中查找本地高速缓存的逻辑地址的第一部分。本地缓存目录返回本地缓存目录中每个集合的集合标识符。每个集合标识符表示较高级别的高速缓存目录中的集合。该机制查找较高级别高速缓存目录中的逻辑地址的第二部分，并将从较高级别高速缓存目录接收的每个绝对地址值与从翻译后备缓冲器接收的绝对地址进行比较，以产生更高级别的高速缓存命中信号。该机制将高级缓存命中信号与每个集合标识符进行比较以产生本地高速缓存命中信号，并且响应于指示本地高速缓存命中的本地高速缓存命中信号，基于本地高速缓存命中信号访问本地高速缓存。

9. 发明授权

US09262320B2 Tracking transactional execution footprint 有权
标题翻译：跟踪事务执行占用
公开(公告)号：US09262320B2
公开(公告)日：2016-02-16
申请号：US13524355
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
IPC分类号： G06F12/08 , G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F12/08 , G06F9/30 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3013 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467 , G06F12/0815 , G06F12/084
摘要： Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended.
摘要翻译：实施例涉及跟踪事务执行足迹。一方面包括接收包括存储数据的存储指令。确定存储指令是否在事务内执行，以有效地将提交存储延迟到共享高速缓存，直到事务完成。存储数据被存储到本地高速缓存中的高速缓存行。如果事务处于活动状态，则缓存行被标记为脏。如果事务异常终止，则在本地缓存中标记为脏的存储数据将无效。如果确定交易已成功结束，则存储的数据将被取消标记。

10. 发明申请

US20130339629A1 TRACKING TRANSACTIONAL EXECUTION FOOTPRINT 有权
标题翻译：跟踪交易执行功能
公开(公告)号：US20130339629A1
公开(公告)日：2013-12-19
申请号：US13524355
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F9/30 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3013 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467 , G06F12/0815 , G06F12/084
摘要： Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended.
摘要翻译：实施例涉及跟踪事务执行足迹。一方面包括接收包括存储数据的存储指令。确定存储指令是否在事务内执行，以有效地将提交存储延迟到共享高速缓存，直到事务完成。存储数据被存储到本地高速缓存中的高速缓存行。如果事务处于活动状态，则缓存行被标记为脏。如果事务异常终止，则在本地缓存中标记为脏的存储数据将无效。如果确定交易已成功结束，则存储的数据将被取消标记。

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