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1. 发明授权

US07368960B2 Circuit and method for monitoring the integrity of a power supply 有权
标题翻译：用于监控电源完整性的电路和方法
公开(公告)号：US07368960B2
公开(公告)日：2008-05-06
申请号：US11153759
申请日：2005-06-15
申请人： Gabriel M. Li , Greg J. Richmond
发明人： Gabriel M. Li , Greg J. Richmond
IPC分类号： H03L7/00
CPC分类号： G06F1/28 , G01R19/16552
摘要： Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.
摘要翻译：本文提供了用于监测电源的完整性的电路和方法，所述电路和方法提供用于诊断复位信号背后的原因的附加资源/信息，并且在一些情况下是电源故障背后的原因。本文描述的第一种方法提供了用于监测提供给一个或多个系统组件的电源电压的电平的示例性步骤。第二种方法描述了用于监测电源（或接地电源）和一个或多个电源引脚之间的电连接的示例性步骤。每种方法涉及监视存储在例如状态寄存器内的一个或多个位的状态。这些方法可以单独使用，也可以彼此结合使用，用于检测功率异常的发生。

2. 发明授权

US07454645B2 Circuit and method for monitoring the status of a clock signal 有权
标题翻译：用于监视时钟信号状态的电路和方法
公开(公告)号：US07454645B2
公开(公告)日：2008-11-18
申请号：US11097527
申请日：2005-03-31
申请人： Gabriel M. Li , Greg J. Richmond , Sangeeta Raman
发明人： Gabriel M. Li , Greg J. Richmond , Sangeeta Raman
IPC分类号： G06F1/00 , G06F1/14
CPC分类号： H03K5/26 , G01R23/005 , G06F1/12 , H03K5/19
摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
摘要翻译：本文提供了一种用于监视时钟信号的状态的电路和方法。通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。

3. 发明授权

US07295051B2 System and method for monitoring a power supply level 有权
公开(公告)号：US07295051B2
公开(公告)日：2007-11-13
申请号：US11153773
申请日：2005-06-15
申请人： Gabriel M. Li , Greg J. Richmond
发明人： Gabriel M. Li , Greg J. Richmond
IPC分类号： H03L7/00 , H03K3/02
CPC分类号： G06F1/28
摘要： A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

4. 发明授权

US07616073B1 Resonator and amplifying oscillator circuit having a high resolution skew-compensated frequency synthesizer integrated on a single substrate 有权
标题翻译：具有集成在单个基板上的高分辨率偏斜补偿频率合成器的谐振器和放大振荡器电路
公开(公告)号：US07616073B1
公开(公告)日：2009-11-10
申请号：US11743727
申请日：2007-05-03
申请人： Babak Taheri , Steve Whelan , Greg J. Richmond
发明人： Babak Taheri , Steve Whelan , Greg J. Richmond
IPC分类号： H03L1/00
CPC分类号： H03C3/0925 , H03B5/04 , H03B5/326 , H03C3/0933 , H03C3/0958 , H03L1/026 , H03L1/027 , H03L7/1976
摘要： An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.
摘要翻译：提供了具有连接到谐振器的振荡放大器电路的振荡器电路。振荡器/放大器和谐振器优选地使用半导体制造工具在单个管芯上制造。与电路一起包括温度传感器或换能器，执行单元，非易失性存储器，调制器和频率合成器，它们都与压电晶体谐振器一起集成在基板上。频率合成器可以优选地包括具有在锁相环的反馈环路中的分频器的锁相环，其中从调制器接收分频值，该调制器从电压获得更精细和更高分辨率的频率选择性控制振荡器，也在锁相环内，作为晶体振荡器的输出。

5. 发明授权

US07433439B1 Apparatus, system, and method for synchronizing signals received by one or more system components 有权
标题翻译：用于同步由一个或多个系统组件接收的信号的装置，系统和方法
公开(公告)号：US07433439B1
公开(公告)日：2008-10-07
申请号：US10325011
申请日：2002-12-20
申请人： Greg J. Richmond
发明人： Greg J. Richmond
IPC分类号： H04L25/00
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/16
摘要： A phase shift apparatus, system and method are described herein for synchronizing output signals upon one or more components of a synchronous system. In one embodiment, the phase shift apparatus may be implemented as a clock generation circuit, which is configured to provide synchronous clocking signals to one or more components of the synchronous system. In another embodiment, the phase shift apparatus may be implemented as a data interface circuit, which is configured to provide error-free data transmission within a synchronous system. In either embodiment, the phase shift apparatus is configured to shift the plurality of signals by programmable first phase shift amounts prior to shifting the plurality of signals by programmable second phase shift amounts. As such, the phase shift apparatus is adapted to substantially eliminate clock skew, data skew and/or jitter, which may otherwise adversely affect the synchronous system. In addition, the phase shift apparatus is adapted to provide a phase resolution, which allows accurate control of such timing delays at substantially any operating frequency.
摘要翻译：本文描述了相移装置，系统和方法，用于使同步系统的一个或多个部件上的输出信号同步。在一个实施例中，相移装置可以被实现为时钟发生电路，其被配置为向同步系统的一个或多个组件提供同步时钟信号。在另一个实施例中，相移装置可以被实现为数据接口电路，其被配置为在同步系统内提供无错误的数据传输。在任一实施例中，相移装置被配置为在通过可编程的第二相移量移位多个信号之前，通过可编程的第一相移量移位多个信号。因此，相移装置适用于基本上消除时钟偏移，数据偏移和/或抖动，否则可能会对同步系统产生不利影响。此外，相移装置适于提供相位分辨率，其允许在基本上任何工作频率下精确地控制这种定时延迟。

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