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1. 外观设计

USD972666S1 Ankle exercise device 有权
公开(公告)号：USD972666S1
公开(公告)日：2022-12-13
申请号：US29788061
申请日：2021-03-03
申请人： Antony Mathew , Amy Rose Thomas , Antony George Mathew
设计人： Antony Mathew , Amy Rose Thomas , Antony George Mathew

2. 发明授权

US08879182B2 Storage media inter-track interference cancellation 有权
标题翻译：存储介质轨道间干扰消除
公开(公告)号：US08879182B2
公开(公告)日：2014-11-04
申请号：US13591937
申请日：2012-08-22
申请人： Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park , Timothy W. Swatosh , Timothy B. Lund , Carl E. Forhan
发明人： Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park , Timothy W. Swatosh , Timothy B. Lund , Carl E. Forhan
IPC分类号： G11B5/09 , G11B20/10 , G11B19/04 , G11B5/012 , G11B20/14 , G11B20/12 , G11B20/18
CPC分类号： G11B5/09 , G11B5/012 , G11B19/045 , G11B20/10046 , G11B20/10212 , G11B20/10462 , G11B20/1217 , G11B20/1423 , G11B2020/10759 , G11B2020/1232 , G11B2020/1298 , G11B2020/183 , G11B2020/185 , G11B2020/1856 , G11B2220/2516
摘要： Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A road channel reads sectors in a desired track of the storage medium. A decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track and a second adjacent track are read. An ITI canceller of the read channel estimates ITI in the read sectors of the desired track corresponding to the selected sectors of each adjacent track and subtracts the estimated ITI of each adjacent track from the data for the sectors of the desired track, providing updated sector data. The ITI cancelled data is replayed to the decoder, which decodes the ITI cancelled data and provides the decoded ITI cancelled data as output of the read channel.
摘要翻译：所描述的实施例提供了从存储介质的期望轨迹读取的一个或多个扇区消除轨道间干扰（ITI）的方法。道路通道读取存储介质的期望轨道中的扇区。读通道的解码器解码读扇区，并且如果从存储介质中错误地恢复读扇区，则读取第一相邻轨道和第二相邻轨道的选定扇区。读通道的ITI消除器估计对应于每个相邻磁道的所选扇区的期望磁道的读扇区中的ITI，并从期望磁道的扇区的数据中减去每个相邻磁道的估计ITI，从而提供更新的扇区数据。 ITI取消的数据被重播到解码器，解码器解码ITI取消的数据，并将解码的ITI取消数据作为读通道的输出。

3. 发明授权

US08773794B2 Systems and methods for block-wise inter-track interference compensation 有权
标题翻译：用于块式轨道间干扰补偿的系统和方法
公开(公告)号：US08773794B2
公开(公告)日：2014-07-08
申请号：US13186213
申请日：2011-07-19
申请人： George Mathew , Jongseung Park , Shaohua Yang , Erich F. Haratsch
发明人： George Mathew , Jongseung Park , Shaohua Yang , Erich F. Haratsch
IPC分类号： G11B5/09
CPC分类号： G11B20/10046 , G11B5/012 , G11B5/09 , G11B19/045 , G11B20/10398 , G11B20/1217 , G11B2020/10759 , G11B2020/1232 , G11B2020/1298 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a block-wise data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set corresponding to a block. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set across the block based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set across the block based at least in part on the previous track data set and the inter-track interference response from the previous track data set.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括数据缓冲器，轨道间干扰响应电路和轨道间干扰信号估计器电路的块状数据处理电路。数据缓冲器可操作以存储对应于块的先前轨道数据集。轨道间干扰响应电路可操作以至少部分地基于先前的轨道数据集和当前轨道数据集来估计来自块的前一轨道数据集的轨道间干扰响应。轨道间干扰信号估计器电路可操作以至少部分地基于先前的轨道数据集和来自前一轨道数据集的轨道间干扰响应来计算跨越块的先前轨道数据集的轨道间干扰。

4. 发明授权

US08749908B2 Systems and methods for sync mark detection 有权
标题翻译：用于同步标记检测的系统和方法
公开(公告)号：US08749908B2
公开(公告)日：2014-06-10
申请号：US13050048
申请日：2011-03-17
申请人： Haitao Xia , Shaohua Yang , George Mathew
发明人： Haitao Xia , Shaohua Yang , George Mathew
IPC分类号： G11B5/09
CPC分类号： G11B5/59616
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括均衡器电路和数据检测电路的数据处理电路。均衡器电路可操作以至少部分地基于滤波器系数对一系列样本进行滤波，并提供相应的一系列滤波样本。数据检测电路包括：核心数据检测器电路和系数确定电路。核心数据检测器电路可操作以对一系列经滤波的样本执行数据检测处理，并提供最可能的路径和下一个最可能的路径。系数确定电路可操作以至少部分地基于最可能的路径和下一个最可能的路径来更新滤波器系数。

5. 发明授权

US08631123B2 Domain based isolation of network ports 有权
标题翻译：基于域的隔离网络端口
公开(公告)号：US08631123B2
公开(公告)日：2014-01-14
申请号：US13006618
申请日：2011-01-14
申请人： Saurabh Desai , George Mathew Koikara , Pruthvi Panyam Nataraj , Guha Prasad Venkataraman , Vidya Ranganathan
发明人： Saurabh Desai , George Mathew Koikara , Pruthvi Panyam Nataraj , Guha Prasad Venkataraman , Vidya Ranganathan
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L63/0236 , H04L63/104
摘要： When an operating system process evaluates a rule for an operation being attempted on a logical network port, the operating system process determines whether the target logical port falls within a range of logical ports, and then determines whether the operation is associated with a permitted domain of the range of logical ports. If the operation is a bind operation, then the process attempting to bind to the target port will be allowed to bind if the target port falls within the range and the operation/process is associated with a permitted domain. Otherwise, the binding operation will not be allowed to proceed.
摘要翻译：当操作系统进程评估在逻辑网络端口上尝试的操作的规则时，操作系统进程确定目标逻辑端口是否落入逻辑端口的范围内，然后确定该操作是否与允许的域逻辑端口的范围。如果操作是绑定操作，则如果目标端口在范围内，并且操作/进程与允许的域相关联，则尝试绑定到目标端口的进程将被允许绑定。否则，将不允许绑定操作继续。

6. 发明授权

US08577855B2 Online file system consistency check 有权
标题翻译：在线文件系统一致性检查
公开(公告)号：US08577855B2
公开(公告)日：2013-11-05
申请号：US12907821
申请日：2010-10-19
申请人： Nagaraj Shyam , Craig Keatley Harmer , George Mathew
发明人： Nagaraj Shyam , Craig Keatley Harmer , George Mathew
IPC分类号： G06F17/30
CPC分类号： G06F17/30171
摘要： A lock is acquired on a data structure. Content in the data structure is read and verified while the lock is held. The lock is then released, and then the file system components that are referred to by the data structure are verified. In essence, a file system consistency check of the file system components is performed offline in the background while the data structure remains accessible.
摘要翻译：在数据结构上获取锁。数据结构中的内容在锁定时被读取和验证。然后释放锁，然后验证数据结构引用的文件系统组件。本质上，文件系统组件的文件系统一致性检查在后台执行，而数据结构仍然可访问。

7. 发明授权

US08526133B2 Systems and methods for user data based fly height calculation 有权
标题翻译：基于用户数据的飞行高度计算的系统和方法
公开(公告)号：US08526133B2
公开(公告)日：2013-09-03
申请号：US13185562
申请日：2011-07-19
申请人： Haitao Xia , George Mathew , Ming Jin , Shaohua Yang
发明人： Haitao Xia , George Mathew , Ming Jin , Shaohua Yang
IPC分类号： G11B21/02
CPC分类号： G11B5/6029
摘要： Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit.
摘要翻译：本发明的各种实施例提供了用于计算和/或修改飞行高度的系统和方法。例如，公开了一种用于计算飞行高度的电路，其包括：第一模式检测器电路，第二模式检测器电路，第一模式飞行高度计算电路，第二模式飞行高度计算电路，第一平均电路，第二平均电路和组合电路。

8. 发明授权

US08379498B2 Systems and methods for track to track phase alignment 有权
标题翻译：轨道跟踪相位对准的系统和方法
公开(公告)号：US08379498B2
公开(公告)日：2013-02-19
申请号：US13186146
申请日：2011-07-19
申请人： George Mathew , Ming Jin , Shaohua Yang , Erich F. Haratsch
发明人： George Mathew , Ming Jin , Shaohua Yang , Erich F. Haratsch
IPC分类号： G11B5/09
CPC分类号： G11B20/10046 , G11B5/012 , G11B5/09 , G11B19/045 , G11B20/10398 , G11B20/1217 , G11B2020/10759 , G11B2020/1232 , G11B2020/1298 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. The sync mark detector circuit operable to identify the first sync pattern in the inter-track interference from the previous track data set in the current track data set.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括数据缓冲器，轨道间干扰响应电路，轨道间干扰信号估计器电路和同步标记检测器电路的数据处理电路。数据缓冲器可操作以存储包括第一同步模式的先前轨迹数据集。轨道间干扰响应电路可用于至少部分地基于先前的轨道数据集和当前轨道数据集来估计来自先前轨道数据集的轨道间干扰响应。当前轨道数据集包括第二同步模式。轨道间干扰信号估计器电路可用于至少部分地基于先前的轨道数据集和来自前一轨道数据集的轨道间干扰响应来计算来自先前轨道数据集的轨道间干扰。同步标记检测器电路可用于识别来自当前轨道数据集中的先前轨道数据集的轨道间干扰中的第一同步模式。

9. 发明授权

US08300349B2 Systems and methods for format efficient calibration for servo data based harmonics calculation 失效
标题翻译：基于伺服数据的谐波计算格式有效校准的系统和方法
公开(公告)号：US08300349B2
公开(公告)日：2012-10-30
申请号：US12851425
申请日：2010-08-05
申请人： George Mathew , Suharli Tedja , Hongwei Song , Robert A. Greene , Yuan Xing Lee
发明人： George Mathew , Suharli Tedja , Hongwei Song , Robert A. Greene , Yuan Xing Lee
IPC分类号： G11B21/02 , G11B5/09
CPC分类号： G11B5/6029 , G11B20/10018 , G11B20/10481 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio.
摘要翻译：本发明的各种实施例提供了用于基于伺服数据的谐波计算的系统和方法。例如，公开了一种用于计算谐波的方法，包括：提供数据处理电路; 在伺服数据处理期间接收从数据源导出的第一数据组; 使用所述第一数据组执行第一谐波计算以产生第一谐波比; 在用户数据处理期间接收从除了前述数据源之外的源得到的第二数据集; 使用所述第二数据组执行二次谐波计算以产生第二谐波比; 以及计算所述第一谐波比与所述第二谐波比的比率。

10. 发明授权

US08295001B2 Systems and methods for low latency noise cancellation 有权
标题翻译：用于低延迟噪声消除的系统和方法
公开(公告)号：US08295001B2
公开(公告)日：2012-10-23
申请号：US12887369
申请日：2010-09-21
申请人： Jingfeng Liu , Haotian Zhang , Hongwei Song , George Mathew
发明人： Jingfeng Liu , Haotian Zhang , Hongwei Song , George Mathew
IPC分类号： G11B5/09 , G11B27/36
CPC分类号： G11B20/10046 , G11B20/10509
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，讨论了包括数据检测器电路，检测器模拟电路和误差计算电路的数据处理电路。数据检测器电路可操作以对从数据输入导出的第一信号执行数据检测处理，以产生检测到的输出。数据模拟电路可操作以处理从数据输入得到的第二信号以产生模拟输出。误差计算电路可用于计算第二信号和从模拟输出得到的第三信号之间的差以产生反馈信号。反馈信号可操作以在随后的时段内修改数据输入。

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