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1. 发明授权

US08176257B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US08176257B2
公开(公告)日：2012-05-08
申请号：US13087974
申请日：2011-04-15
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

2. 发明授权

US07970970B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址开关，每个代理队列较浅
公开(公告)号：US07970970B2
公开(公告)日：2011-06-28
申请号：US12787865
申请日：2010-05-26
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

3. 发明授权

US07861107B1 Dual access pathways to serially-connected mass data storage units 有权
标题翻译：串行连接的大容量数据存储单元的双通道
公开(公告)号：US07861107B1
公开(公告)日：2010-12-28
申请号：US12506887
申请日：2009-07-21
申请人： Sue Coatney , George Kong , Doug Coatney
发明人： Sue Coatney , George Kong , Doug Coatney
IPC分类号： G06F11/00
CPC分类号： G06F11/2035 , G06F11/201 , G06F11/2033 , G06F11/2046 , G06F11/2089
摘要： A group of data storage units are serially connected in a sequential data communication path to communicate read and write operations to first and second interfaces of each data storage unit in the group. A data management computer device (“filer”) manages read and write operations of the data storage units of the group through an adapter of the filer. Main and redundant primary communication pathway connectors extend from the filer to the interfaces of the data storage unit, thereby establishing redundancy through multiple pathways to communicate the read and write operations to the data storage units of the group. Main and redundant secondary communication pathway connectors extend from partner filers to the groups of data storage units associated with each partner filer, thereby further enhancing redundancy.
摘要翻译：一组数据存储单元在顺序数据通信路径中串行连接，以将读取和写入操作传送到组中每个数据存储单元的第一和第二接口。数据管理计算机设备（“filer”）通过文件管理器的适配器来管理该组的数据存储单元的读和写操作。主要和冗余的主要通信路径连接器从文件管理器延伸到数据存储单元的接口，从而通过多个路径建立冗余，以将读取和写入操作传达到组的数据存储单元。主要和冗余的二次通信路径连接器从伙伴文件管理器延伸到与每个合作伙伴文件管理器相关联的数据存储单元组，从而进一步增强冗余。

4. 发明授权

US07269682B2 Segmented interconnect for connecting multiple agents in a system 有权
标题翻译：用于连接系统中多个代理的分段互连
公开(公告)号：US07269682B2
公开(公告)日：2007-09-11
申请号：US11201573
申请日：2005-08-11
申请人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
发明人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00 , G06F13/36 , H04L12/00 , H04L12/12
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

5. 发明授权

US07624235B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US07624235B2
公开(公告)日：2009-11-24
申请号：US11565391
申请日：2006-11-30
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

6. 发明申请

US20090055568A1 Non-blocking Address Switch with Shallow Per Agent Queues 有权
标题翻译：非阻塞地址交换机与每个代理队列相邻
公开(公告)号：US20090055568A1
公开(公告)日：2009-02-26
申请号：US12263255
申请日：2008-10-31
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/14
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

7. 发明授权

US08621059B1 System and method for distributing enclosure services data to coordinate shared storage 有权
标题翻译：用于分配机箱服务数据以协调共享存储的系统和方法
公开(公告)号：US08621059B1
公开(公告)日：2013-12-31
申请号：US13151100
申请日：2011-06-01
申请人： George Kong , Anthony F. Aiello , Radek Aster , Randal Thelen
发明人： George Kong , Anthony F. Aiello , Radek Aster , Randal Thelen
IPC分类号： G06F15/173 , G06F7/00 , G06F13/00
CPC分类号： G06F13/385 , G06F2213/0036 , G06F2213/0058
摘要： A system and method for distributing enclosure services information is provided. A plurality of storage systems that are operatively interconnected with one or more intermediate networking devices and/or disk shelves are modified to include a target device driver module that is adapted to receive and process target commands from other storage systems to enable the sharing and retrieval of SES information from a storage shelf's master storage system.
摘要翻译：提供了一种用于分发机箱服务信息的系统和方法。与一个或多个中间联网设备和/或盘架可操作地互连的多个存储系统被修改为包括目标设备驱动器模块，其适于从其他存储系统接收和处理目标命令，以使得能够共享和检索 SES信息来自存储架的主存储系统。

8. 发明授权

US08099624B1 Recovery mechanism for I/O module using out-of-band control path 有权
标题翻译：使用带外控制路径的I / O模块的恢复机制
公开(公告)号：US08099624B1
公开(公告)日：2012-01-17
申请号：US12557441
申请日：2009-09-10
申请人： Mayank Saxena , George Kong , Wanye Booth , James Lin , Radek Aster
发明人： Mayank Saxena , George Kong , Wanye Booth , James Lin , Radek Aster
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0727 , G06F11/108
摘要： A storage system includes a storage server and a storage subsystem having an I/O module coupled to disks. The storage server includes a storage adapter coupled to the I/O module creating an in-band (data) path to access data stored on the disks. The storage server sends a data command through the in-band path to the I/O module for accessing the data stored on the disks. The storage server further includes a network adapter coupled to the I/O module creating an out-of-band control path to control the I/O module. The storage server detects through the in-band path that the I/O module is non-responsive to a data command and automatically changes the behavior of the I/O module (e.g., resets the I/O module) through the out-of-band control path to recover the non-responsive I/O module. The storage server also collects and outputs status data of the I/O module through the out-of-band control path.
摘要翻译：存储系统包括存储服务器和具有耦合到盘的I / O模块的存储子系统。存储服务器包括耦合到I / O模块的存储适配器，创建带内（数据）路径以访问存储在磁盘上的数据。存储服务器通过带内路径将数据命令发送到I / O模块，以访问存储在磁盘上的数据。存储服务器还包括耦合到I / O模块的网络适配器，其创建带外控制路径以控制I / O模块。存储服务器通过带内路径检测I / O模块对数据命令无响应，并自动更改I / O模块的行为（例如，复位I / O模块），通过外部带控制路径来恢复非响应I / O模块。存储服务器还通过带外控制路径收集和输出I / O模块的状态数据。

9. 发明授权

US08019842B1 System and method for distributing enclosure services data to coordinate shared storage 有权
标题翻译：用于分配机箱服务数据以协调共享存储的系统和方法
公开(公告)号：US08019842B1
公开(公告)日：2011-09-13
申请号：US11075618
申请日：2005-03-08
申请人： George Kong , Anthony F. Aiello , Radek Aster , Randal Thelen
发明人： George Kong , Anthony F. Aiello , Radek Aster , Randal Thelen
IPC分类号： G06F15/173 , G06F7/00 , G06F13/00
CPC分类号： G06F13/385 , G06F2213/0036 , G06F2213/0058
摘要： A system and method for distributing enclosure services information is provided. A plurality of storage systems that are operatively interconnected with one or more intermediate networking devices and/or disk shelves are modified to include a target device driver module that is adapted to receive and process target commands from other storage systems to enable the sharing and retrieval of SES information from a storage shelf's master storage system.
摘要翻译：提供了一种用于分发机箱服务信息的系统和方法。与一个或多个中间联网设备和/或盘架可操作地互连的多个存储系统被修改为包括目标设备驱动器模块，其适于从其他存储系统接收和处理目标命令，以使得能够共享和检索 SES信息来自存储架的主存储系统。

10. 发明申请

US20110197033A1 Cache Used Both as Cache and Staging Buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US20110197033A1
公开(公告)日：2011-08-11
申请号：US13087974
申请日：2011-04-15
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

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