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1. 发明授权

US06980472B2 Device and method to read a 2-transistor flash memory cell 有权
标题翻译：读取2晶体管闪存单元的器件和方法
公开(公告)号：US06980472B2
公开(公告)日：2005-12-27
申请号：US10498449
申请日：2002-12-05
申请人： Anthonie Meindert Herman Ditewig , Franciscus Petrus Widdershoven , Roger Cuppens
发明人： Anthonie Meindert Herman Ditewig , Franciscus Petrus Widdershoven , Roger Cuppens
IPC分类号： G11C16/06 , G11C5/00 , G11C16/02 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26
摘要： The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells.A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage.A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.
摘要翻译：本发明涉及电子存储器，更具体地说，涉及一种读取紧凑型2-晶体管闪存单元的内容的改进方法和装置。提供读取2晶体管闪存单元1的方法。存储单元1包括具有存储栅极6的存储晶体管2和具有选择栅极7的选择晶体管3。该方法包括在选择栅极7从第一电压切换到第二电压的同时使存储栅极6浮动，由此第一电压低于第二电压。根据本发明的装置包括用于在选择栅极7从第一电压切换到第二电压时使存储栅极6离开的开关电路，第一电压低于第二电压。

2. 发明授权

US08679966B2 Semiconductor device having Au-Cu electrodes, and method of manufacturing semiconductor device 有权
标题翻译：具有Au-Cu电极的半导体器件及半导体器件的制造方法
公开(公告)号：US08679966B2
公开(公告)日：2014-03-25
申请号：US13568695
申请日：2012-08-07
申请人： David Van Steenwinckel , Thomas Merelle , Franciscus Petrus Widdershoven , Viet Hoang Nguyen , Dimitri Soccoi , Jan Leo Dominique Fransaer
发明人： David Van Steenwinckel , Thomas Merelle , Franciscus Petrus Widdershoven , Viet Hoang Nguyen , Dimitri Soccoi , Jan Leo Dominique Fransaer
IPC分类号： H01L21/4763
CPC分类号： G01N27/4145 , G01N27/3275 , H01L29/66
摘要： A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au—Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au—Cu alloy electrodes is also disclosed.
摘要翻译：一种制造生物传感器半导体器件的方法，其中在器件的主表面上的铜电极被改性以形成Au-Cu合金电极。通过在器件上沉积金层，然后对该器件进行热处理以促进金和电极铜之间的相互扩散来实现这种修改。从器件的表面去除合金金铜，留下暴露的电极。与常规铜电极的情况相比，电极与生物传感器装置的进一步处理更好地兼容，并且处理窗口比金盖铜电极宽。还公开了具有Au-Cu合金电极的生物传感器半导体器件。

3. 发明申请

US20080318375A1 Method of Fabricating a Duel-Gate Fet 有权
标题翻译：制造决斗门的方法
公开(公告)号：US20080318375A1
公开(公告)日：2008-12-25
申请号：US11815100
申请日：2006-01-23
申请人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
发明人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.
摘要翻译：本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法，其具有非常小且可重现的鳍，其间距和宽度都小于可以用光刻技术获得的。在基板（1）上的突起（2）上形成第一层（3）和第二层（4），然后露出突起（2）的上表面。相对于突起（2）和第二层（4），第一层（3）的一部分被选择性地去除，从而形成翅片（6）和沟槽（5）。还提出了形成多个翅片（6）和沟槽（5）的方法。通过在沟槽（5）中形成栅电极（7）和源极和漏极区域来产生双栅极FET。此外，提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。

4. 发明申请

US20080259576A1 Electronic Device or Circuit and Method for Fabricating the Same 审中-公开
标题翻译：电子设备或电路及其制造方法
公开(公告)号：US20080259576A1
公开(公告)日：2008-10-23
申请号：US12089255
申请日：2006-09-29
申请人： Mark Thomas Johnson , Adrianus Sempel , Franciscus Petrus Widdershoven
发明人： Mark Thomas Johnson , Adrianus Sempel , Franciscus Petrus Widdershoven
IPC分类号： H01L21/58 , H05K1/00
CPC分类号： H05K1/189 , H05K1/028 , H05K3/0058 , H05K3/281 , H05K2201/052 , H05K2201/055
摘要： A method for fabricating an electronic device or circuit, respectively, comprises providing a flexible substrate (1), defining onto the flexible substrate (1) electric components (2, 3, 3′, 3″, 3′″, 7, 11, 12) and interconnects (8), introducing out breaks (4, 4′, 4″, 4a-4s) in the flexible substrate (1) between the electric components and/or interconnects, and forming the flexible substrate (1) into a deformed configuration by deforming, particularly folding, parts of the flexible substrate as determined by the breaks (4, 4′, 4″, 4a-4s).
摘要翻译：一种分别制造电子设备或电路的方法，包括提供柔性基板（1），其限定在柔性基板（1）上，电气部件（2,3,3'，3“，3”，7“ 11）和互连（8），在电气部件和/或互连之间引入柔性基板（1）中的断裂（4,4'，4“，4a-4s），并形成柔性基板（4,4'，4“，4a-4s）确定的柔性基板的部分变形（特别是折叠）变形为变形构型。

5. 发明授权

US07307267B2 Electric device with phase change material and parallel heater 有权
标题翻译：具有相变材料和并联加热器的电气设备
公开(公告)号：US07307267B2
公开(公告)日：2007-12-11
申请号：US10539102
申请日：2003-12-05
申请人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
发明人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/124 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1691 , Y10S438/90
摘要： The electric device (1, 100) has a body (2, 102) having a resistor (7, 107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 107) has a first electrical resistance when the phase change material is in the first phase and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The body (2, 102) further has a heating element (6, 106) being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (6, 106) is arranged in parallel with the resistor (7, 107).
摘要翻译：电气设备（1,100）具有主体（2,102），该主体具有电阻器（7,107），该电阻器包括可在第一相位和第二相位之间变化的相变材料。当相变材料处于第二相时，当相变材料处于第一相位时，电阻器（7,107）具有第一电阻，并且具有与第一电阻不同的第二电阻。主体（2,102）还具有加热元件（6,106），该加热元件能够传导电流以实现从第一相到第二相的转变。加热元件（6,106）与电阻器（7,107）平行设置。

6. 发明授权

US07214579B2 Self-aligned 2-bit “double poly CMP” flash memory cell 有权
标题翻译：自对准2位“双多晶CMP”闪存单元
公开(公告)号：US07214579B2
公开(公告)日：2007-05-08
申请号：US10532292
申请日：2002-08-18
申请人： Franciscus Petrus Widdershoven , Michiel Jos Van Duuren
发明人： Franciscus Petrus Widdershoven , Michiel Jos Van Duuren
IPC分类号： H01L21/8239
CPC分类号： G11C16/0458 , H01L27/115 , H01L27/11521
摘要： Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (8), a capping layer (6) and side-wall spacers (10), the cell further including source and drain contacts (22), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer (12) with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (12); defining the intermediate access gate (AG) in the planarized poly-Si layer (14) by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.
摘要翻译：存储单元的制造，该单元包括第一浮栅堆叠（A），第二浮栅堆叠（B）和中间存取栅极（AG），所述浮栅叠层（A，B）包括第一栅氧化层 4），浮动栅极（FG），控制栅极（CG; CG1，CGu），多晶硅间介电层（8），封盖层（6）和侧壁间隔物（10）漏极触点（22），其中所述制造包括：在相同的处理步骤中限定所述浮栅堆叠以具有相同的高度; 在浮栅上沉积堆叠具有比浮栅堆叠高度更大的厚度的多晶硅层（12）; 平面化多晶硅层（12）; 通过在浮栅堆叠之间的多晶硅层和多晶硅蚀刻步骤之间的存取栅掩模步骤，在平坦化的多晶硅层（14）中限定中间栅极（AG）。

7. 发明授权

US07177974B2 Data processing device with a memory location in which data is stored according to a WOM (write once memory) code 失效
标题翻译：具有根据WOM（一次写入存储器）代码存储数据的存储器位置的数据处理设备
公开(公告)号：US07177974B2
公开(公告)日：2007-02-13
申请号：US10755238
申请日：2004-01-12
申请人： Sebastian Egner , Franciscus Petrus Widdershoven
发明人： Sebastian Egner , Franciscus Petrus Widdershoven
IPC分类号： G11C17/00 , G11C7/10
CPC分类号： G11C17/005
摘要： A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit updates to the WOM (Write Once Memory) codeword. If no feasible single bit update is possible, feasible two-bit updates are considered. Under control of the new data values a connection circuit routes feasibility signals for various updates, that signal the single-bit feasibility of the updates. Routing brings together pairs of feasibility signals for updates that together produce a WOM codeword that encodes the new data value. A pair is selected in which both feasibility signals indicate feasibility and the codeword is updated according to the updates involved in the pair. Preferably, the routing is realized with a connection circuit that comprises a number of layers of subcircuits, each routing the feasibility signals dependent on a respective bit of the new dataword. Also preferably, the WOM code is designed so that each of a number of updates to the data word can be realized by setting singles ones of a plurality of bits.
摘要翻译：设备包含存储编码连续几代数据值的WOM码字的存储器。当代码字必须被更新以表示新的数据值时，设备通过对WOM（一次写入存储器）码字的可行单位更新来确定可以实现数据字的哪些更新。如果没有可行的单比特更新是可行的，则考虑可行的两比特更新。在新的数据值的控制下，一个连接电路可以路由各种更新的可行性信号，这些信号表明更新的单位可行性。路由汇总了可用信号对，用于一起生成编码新数据值的WOM码字的更新。选择一对，其中两个可行性信号指示可行性，并且根据该对中涉及的更新来更新码字。优选地，路由通过包括多个子电路层的连接电路实现，每个子电路依赖于新数据字的相应位来路由可行性信号。还优选地，WOM码被设计为使得可以通过设置多个比特的单个数目来实现数据字的多个更新中的每一个。

8. 发明授权

US07119353B2 Electric device with phase change material and method of manufacturing the same 有权
标题翻译：具有相变材料的电气装置及其制造方法
公开(公告)号：US07119353B2
公开(公告)日：2006-10-10
申请号：US10539101
申请日：2003-12-05
申请人： Martijn Henri Richard Lankhorst , Franciscus Petrus Widdershoven , Robertus Adrianus Maria Wolters , Wilhelmus Sebastianus Marcus Maria Ketelaars , Erwin Rinaldo Meinders
发明人： Martijn Henri Richard Lankhorst , Franciscus Petrus Widdershoven , Robertus Adrianus Maria Wolters , Wilhelmus Sebastianus Marcus Maria Ketelaars , Erwin Rinaldo Meinders
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , H01L27/2436 , H01L27/2463 , H01L45/1226 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： The electric device (100) has a body (102) having a resistor (107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (107) has a first electrical resistance when the phase change material is in the first phase, and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The phase change material constitutes a conductive path between a first contact area and a second contact area. A cross-section of the conductive path is smaller than the first contact area and the second contact area. The body (102) may further have a heating element 106 being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (106) is preferably arranged in parallel with the resistor (107).
摘要翻译：电气设备（100）具有主体（102），其具有电阻器（107），该电阻器包括可在第一相位和第二相位之间变化的相变材料。当相变材料处于第二相时，电阻器（107）具有第一电阻，当相变材料处于第一相位时，具有不同于第一电阻的第二电阻。相变材料构成第一接触区域和第二接触区域之间的导电路径。导电路径的横截面小于第一接触区域和第二接触区域。主体（102）还可以具有加热元件106，该加热元件能够传导电流以实现从第一相到第二相的转变。加热元件（106）优选地与电阻器（107）并联布置。

9. 发明授权

US06984558B2 Method of manufacturing a semiconductor device with non-volatile memory comprising a memory cell with an access gate and with a control gate and a charge storage region 失效
标题翻译：制造具有非易失性存储器的半导体器件的方法，包括具有存取栅极的存储单元以及控制栅极和电荷存储区域
公开(公告)号：US06984558B2
公开(公告)日：2006-01-10
申请号：US10485496
申请日：2002-06-04
申请人： Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： Method of manufacturing a semiconductor device comprising a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory comprising a memory cell with a gate structure (4) with an access gate (19) and a gate structure (3) with a control gate (5) and a charge storage region situated between the control gate (5) and the semiconductor body (1), such as a floating gate (6). In this method on the surface (2) of the semiconductor body (1) a first one of said gate structures is formed with side walls (10) extending substantially perpendicular to the surface, a conductive layer is deposited (13) on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining the first gate structure. Said patterning of the planarized conductive layer is performed in that the planarized conductive layer (14) is etched back so as to expose an upper portion (15) of the side walls of the first gate structure, a spacer (18) is formed on the exposed upper portion (15) of the side walls of first gate structure and the conductive layer (16) is etched anisotropically using the spacer as a mask. Thus very small memory cells can be realized.
摘要翻译：一种制造半导体器件的方法，包括：半导体本体（1），其在表面（2）处设置有非易失性存储器，所述非易失性存储器包括具有栅极结构（4）的存储单元，所述存储单元具有存取栅极（19）和栅极结构（5）和位于控制栅极（5）和半导体本体（1）之间的电荷存储区域（例如浮动栅极）。在这种方法中，在半导体本体（1）的表面（2）上，第一个所述栅极结构形成有大致垂直于所述表面延伸的侧壁（10），导电层被沉积（13）所述第一栅极结构，对导电层进行平坦化处理，直到第一栅极结构暴露，并且将如此平坦化的导电层图案化，以形成与第一栅极结构相邻的另一栅极结构的至少一部分。平面化导电层的所述图案化是以平坦化的导电层（14）被回蚀以便露出第一栅极结构的侧壁的上部（15）来实现的，间隔物（18）形成在使用间隔物作为掩模，各向异性地蚀刻第一栅极结构的侧壁的暴露的上部（15）和导电层（16）。因此，可以实现非常小的存储单元。

10. 发明申请

US20130207206A1 SEMICONDUCTOR DEVICE HAVING AU-CU ELECTRODES, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：具有AU-CU电极的半导体器件及制造半导体器件的方法
公开(公告)号：US20130207206A1
公开(公告)日：2013-08-15
申请号：US13568695
申请日：2012-08-07
申请人： David VAN STEENWINCKEL , Thomas MERELLE , Franciscus Petrus WIDDERSHOVEN , Viet Hoang NGUYEN , Dimitri SOCCOl , Jan Leo Dominique FRANSAER
发明人： David VAN STEENWINCKEL , Thomas MERELLE , Franciscus Petrus WIDDERSHOVEN , Viet Hoang NGUYEN , Dimitri SOCCOl , Jan Leo Dominique FRANSAER
IPC分类号： H01L29/66
CPC分类号： G01N27/4145 , G01N27/3275 , H01L29/66
摘要： A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au—Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au—Cu alloy electrodes is also disclosed.
摘要翻译：一种制造生物传感器半导体器件的方法，其中在器件的主表面上的铜电极被改性以形成Au-Cu合金电极。通过在器件上沉积金层，然后对该器件进行热处理以促进金和电极铜之间的相互扩散来实现这种修改。从器件的表面去除合金金铜，留下暴露的电极。与常规铜电极的情况相比，电极与生物传感器装置的进一步处理更好地兼容，并且处理窗口比金盖铜电极宽。还公开了具有Au-Cu合金电极的生物传感器半导体器件。

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