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    • 2. 发明申请
    • Non-volatile storage
    • 非易失性存储
    • US20080098157A1
    • 2008-04-24
    • US11585007
    • 2006-10-23
    • J. Michael AndrewarthaJames HessDavid MaciorowskiEdward A. Cross
    • J. Michael AndrewarthaJames HessDavid MaciorowskiEdward A. Cross
    • G06F12/00
    • G06F12/0804G06F12/0246G06F12/08
    • One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.
    • 非易失性存储器系统的一个实施例包括块可访问的非易失性存储器,被处理器作为处理器的存储器地址空间的一部分被布置为可被线性地寻址的随机存取存储器,以便由处理器读取和写入;以及 插入在块可访问非易失性存储器和随机存取存储器之间的逻辑,并且被布置为将块中的随机存取存储器的内容的部分写入到非易失性块可访问存储器的块中。 逻辑被布置为监视对随机存取存储器的处理器写入,并且将非易失性块可访问存储器中的最新副本不同的随机存取存储器块写入非易失性块可访问存储器 。
    • 4. 发明授权
    • Loadshedding uninterruptible power supply
    • 负载不间断电源
    • US06854065B2
    • 2005-02-08
    • US09918767
    • 2001-07-30
    • Robert B. SmithBradley D. WinickEdward A Cross
    • Robert B. SmithBradley D. WinickEdward A Cross
    • H02J9/06G06F1/26G06F1/30
    • G06F1/30G06F1/263
    • A dual power source system includes a first power source and a second power source operably coupled with an electrical device, as well as a switching mechanism capable of selecting between the first and second power sources. An uninterruptible power supply (UPS) is place in line with one of the first and second power sources leading to the electrical device. Sense circuitry is capable of identifying a power failure condition in either the first or second power sources. A controller utilizes signals from the sense circuitry to selectively switch between the first and second power sources while configuring the UPS in a manner of providing for a plurality of operational states that accommodate the electrical device with operational power despite any combination of power failures in the first and second power sources.
    • 双电源系统包括可操作地与电气设备耦合的第一电源和第二电源,以及能够在第一和第二电源之间进行选择的开关机构。 不间断电源(UPS)与通向电气设备的第一和第二电源之一配合。 检测电路能够识别第一或第二电源中的电源故障状况。 控制器利用来自感测电路的信号来选择性地在第一和第二电源之间切换,同时以提供容纳电气设备的多个操作状态的方式配置UPS,尽管在第一和第二电源中的电源故障的任何组合 和第二电源。
    • 6. 发明授权
    • Non-volatile storage for backing up volatile storage
    • 用于备份易失性存储的非易失性存储
    • US07694091B2
    • 2010-04-06
    • US11585007
    • 2006-10-23
    • J. Michael AndrewarthaJames HessDavid MaciorowskiEdward A. Cross
    • J. Michael AndrewarthaJames HessDavid MaciorowskiEdward A. Cross
    • G06F11/08G06F12/16
    • G06F12/0804G06F12/0246G06F12/08
    • One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.
    • 非易失性存储器系统的一个实施例包括块可访问的非易失性存储器,被处理器作为处理器的存储器地址空间的一部分被布置为可被线性地寻址的随机存取存储器,以便由处理器读取和写入;以及 插入在块可访问非易失性存储器和随机存取存储器之间的逻辑,并且被布置为将块中的随机存取存储器的内容的部分写入到非易失性块可访问存储器的块中。 逻辑被布置为监视对随机存取存储器的处理器写入,并且将非易失性块可访问存储器中的最新副本不同的随机存取存储器块写入非易失性块可访问存储器 。
    • 7. 发明授权
    • Method and apparatus for ascertaining the status of multiple devices simultaneously over a data bus
    • 用于通过数据总线同时确定多个设备的状态的方法和装置
    • US06912607B2
    • 2005-06-28
    • US10068029
    • 2002-02-06
    • Robert B. SmithEdward A Cross
    • Robert B. SmithEdward A Cross
    • G06F13/42G06F13/00
    • G06F13/4291
    • Techniques are provided for simultaneously ascertaining the status of a plurality of devices coupled to a data bus. A master device transmits at least one status request message over the data bus to a plurality of slave devices. In response, the plurality of slave devices transmit to the master device a status indicator message including a plurality of status indicators indicating statuses of the plurality of slave devices. The master device receives the status indicator message and ascertains the status of at least some of the plurality of slave devices by examining the status indicators. The status request message and/or status indicator message may be a message defined according to a protocol associated with the data bus. The data bus may, for example, be a serial data bus such as an I2C bus.
    • 提供了用于同时确定耦合到数据总线的多个设备的状态的技术。 主设备通过数据总线将至少一个状态请求消息发送到多个从设备。 作为响应,多个从设备向主设备发送包括指示多个从设备的状态的多个状态指示符的状态指示符消息。 主设备通过检查状态指示器来接收状态指示符消息并确定多个从设备中的至少一些从设备的状态。 状态请求消息和/或状态指示符消息可以是根据与数据总线相关联的协议定义的消息。 数据总线可以例如是串行数据总线,例如I C总线。
    • 8. 发明授权
    • System for detection and routing of platform events in a multi-cell computer
    • 用于多小区计算机中的平台事件的检测和路由的系统
    • US06910142B2
    • 2005-06-21
    • US09917413
    • 2001-07-28
    • Edward A CrossMichael S AllisonChristopher S Kroeger
    • Edward A CrossMichael S AllisonChristopher S Kroeger
    • G06F3/00H04L12/24G06F1/32G06F13/00H05K7/10
    • G05B19/0428G05B2219/24025
    • A system for providing notification, to the associated operating system, of removal and replacement of I/O devices during operation of a multiprocessor computer system running multiple operating systems. The system includes a plurality of cells, each containing multiple RISC processors, low-level I/O firmware, a local service processor, scratch RAM, external registers, a memory and I/O manager, and interfacing hardware. Each partition comprises one or more cells and runs its own operating system (OS). Each cell is connected to a peripheral backplane containing a plurality of peripheral I/O card slots via a switch on the system backplane, which also connects the cell to a supervisory processor, which sends card slot status information to the appropriate cell. Each I/O (typically PCI) card slot has an associated latch which provides an indication, to the supervisory processor, that a platform event has occurred. Platform events include inserting or removing an I/O (peripheral device interface) card to/from a card slot, and opening an access panel that provides access to the I/O cards.
    • 在运行多个操作系统的多处理器计算机系统的操作期间向相关联的操作系统提供对I / O设备的移除和替换的通知的系统。 该系统包括多个单元,每个单元包含多个RISC处理器,低级I / O固件,本地服务处理器,临时RAM,外部寄存器,存储器和I / O管理器以及接口硬件。 每个分区包括一个或多个单元并运行其自己的操作系统(OS)。 每个小区经由系统背板上的交换机连接到包含多个外围I / O卡插槽的外围背板,该外部设备也将小区连接到监控处理器,监控处理器将卡槽状态信息发送到适当的小区。 每个I / O(通常为PCI)卡槽具有相关联的锁存器,其向监控处理器提供已发生平台事件的指示。 平台事件包括在卡插槽中插入或取出I / O(外围设备接口)卡,并打开提供对I / O卡的访问的访问面板。
    • 10. 发明授权
    • Field-replaceable unit revision compatibility
    • 现场可更换单元修订兼容性
    • US07725892B2
    • 2010-05-25
    • US10610657
    • 2003-07-01
    • Daniel V. ZilavyGerald J. Kaufman, Jr.Edward A. Cross
    • Daniel V. ZilavyGerald J. Kaufman, Jr.Edward A. Cross
    • G06F9/44
    • G06F8/71G06F9/4411
    • A method for use in a computer system includes a first revision compatibility descriptor identifying a first plurality of compatible combinations of field-programmable unit codes. The method includes steps of: (A) determining whether the first revision compatibility descriptor identifies first field-programmable unit code for use in a first field-programmable unit as being compatible with the computer system; and (B) if the first revision compatibility descriptor does not identify the first field-programmable unit code as being compatible with the computer system, performing a step of updating the first revision compatibility descriptor to identify the first field-programmable unit code as being compatible with the computer system.
    • 一种在计算机系统中使用的方法包括识别现场可编程单元代码的第一多个兼容组合的第一修订兼容性描述符。 该方法包括以下步骤:(A)确定第一修订兼容性描述符是否识别用于第一现场可编程单元的第一现场可编程单元代码与计算机系统兼容; 以及(B)如果所述第一修订兼容性描述符不将所述第一现场可编程单元代码识别为与所述计算机系统兼容,则执行更新所述第一修订兼容性描述符以识别所述第一现场可编程单元代码为兼容性的步骤 与计算机系统。