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1. 发明授权

US08482994B2 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取方法和与其相关联的系统的半导体器件
公开(公告)号：US08482994B2
公开(公告)日：2013-07-09
申请号：US13064476
申请日：2011-03-28
申请人： Kwang-Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang-Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G11C11/34
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
摘要翻译：一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

2. 发明申请

US20110179237A1 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取方法和与其相关联的系统的半导体器件
公开(公告)号：US20110179237A1
公开(公告)日：2011-07-21
申请号：US13064476
申请日：2011-03-28
申请人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G06F12/00
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
摘要翻译：一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

3. 发明授权

US07920432B2 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
公开(公告)号：US07920432B2
公开(公告)日：2011-04-05
申请号：US12292897
申请日：2008-11-28
申请人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G11C7/00
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

4. 发明申请

US20090257292A1 Semiconductor device having resistance based memory array, method of reading, and writing, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件
公开(公告)号：US20090257292A1
公开(公告)日：2009-10-15
申请号：US12292897
申请日：2008-11-28
申请人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G11C7/22
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
摘要翻译：一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

5. 发明授权

US08588010B2 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 有权
公开(公告)号：US08588010B2
公开(公告)日：2013-11-19
申请号：US12929349
申请日：2011-01-18
申请人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
发明人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
IPC分类号： G11C7/22
CPC分类号： G11C13/0064 , G11C7/1078 , G11C7/1096 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C15/00 , G11C2013/0078 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

6. 发明申请

US20110110172A1 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 有权
公开(公告)号：US20110110172A1
公开(公告)日：2011-05-12
申请号：US12929349
申请日：2011-01-18
申请人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
发明人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C13/0064 , G11C7/1078 , G11C7/1096 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C15/00 , G11C2013/0078 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

7. 发明申请

US20090141549A1 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件
公开(公告)号：US20090141549A1
公开(公告)日：2009-06-04
申请号：US12292890
申请日：2008-11-28
申请人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
发明人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
IPC分类号： G11C11/46 , G11C7/10 , G11C15/00
CPC分类号： G11C13/0064 , G11C7/1078 , G11C7/1096 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C15/00 , G11C2013/0078 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.
摘要翻译：至少一个实施例包括非易失性存储单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器以及被配置为将数据写入到非易失性存储单元阵列中的写入单元。写单元被配置为执行数据的写入，使得在被写入缓冲器之前，每个数据将在非易失性存储器中已经达到稳定的存储状态。

8. 发明授权

US07894277B2 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件
公开(公告)号：US07894277B2
公开(公告)日：2011-02-22
申请号：US12292890
申请日：2008-11-28
申请人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
发明人： Kwang Jin Lee , Du Eung Kim , Hye Jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C7/1078 , G11C7/1096 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C15/00 , G11C2013/0078 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.
摘要翻译：至少一个实施例包括非易失性存储单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器以及被配置为将数据写入到非易失性存储单元阵列中的写入单元。写单元被配置为执行数据的写入，使得在被写入缓冲器之前，每个数据将在非易失性存储器中已经达到稳定的存储状态。

9. 发明授权

US06459642B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06459642B1
公开(公告)日：2002-10-01
申请号：US09703820
申请日：2000-11-01
申请人： Beak Hyung Cho , Du Eung Kim , Jong Pil Son
发明人： Beak Hyung Cho , Du Eung Kim , Jong Pil Son
IPC分类号： G11C700
CPC分类号： G11C29/83 , G11C5/14 , G11C29/832
摘要： The invention discloses a semiconductor memory device in which faulty cells causing standby current failure will be replaced with redundancy cells. The semiconductor memory device includes: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines included in the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines providing supply voltage to faulty cells and power source at an occurrence of faulty cells causing standby current failure. At this time, the cell power lines of the cell blocks are arranged in an identical direction to word lines; the row decoder circuits are respectively arranged between two neighboring cell blocks; and the cell power repairing circuits are respectively arranged between the cell blocks of the memory cell array, thereby reducing the size of a chip.
摘要翻译：本发明公开了一种半导体存储器件，其中引起备用电流故障的故障单元将被替换为冗余单元。半导体存储器件包括：多个字线，多个位线，连接在字线和用于存储数据的位线之间的多个单元，以及具有多个单元电力的多个单元块的存储单元阵列为电池提供电源电压的线路; 多个行解码器电路，用于解码外部行地址并产生用于包括在单元块中的预定字线的选择信号; 以及多个单元电力修复电路，用于在出现故障单元并导致待机电流故障时，选择性地阻塞在故障单元和电源之间提供电源电压的单元电源线之间。此时，单元块的单元电力线被排列成与字线相同的方向; 行解码器电路分别布置在两个相邻的单元块之间; 并且电池功率修复电路分别布置在存储单元阵列的单元块之间，从而减小芯片的尺寸。

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