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1. 发明授权

US4731589A Constant current load and level shifter circuitry 失效
标题翻译：恒流负载和电平转换电路
公开(公告)号：US4731589A
公开(公告)日：1988-03-15
申请号：US889209
申请日：1986-07-25
申请人： Donald R. Preslar
发明人： Donald R. Preslar
IPC分类号： H03F3/30 , H03F3/45 , H03F3/26
CPC分类号： H03F3/3096 , H03F3/45071
摘要： Level shifter circuitry, as for an operational amplifier, imposes no current load on the preceding amplifier stage associated with its level shifter function. A common-collector-amplifier first transistor has base and emitter connections to the input and output terminals of the level shifter. A second transistor of similar conductivity type and common-collector forward current gain has its base electrode connected through a first current mirror amplifier to the input terminal of the level shifter and has its emitter electrode connected through a second current mirror amplifier to the output terminal of the level shifter. The first and second current mirror amplifiers have similar current gains. The first current mirror amplifier may also be incorporated in apparatus for supplying constant current loading to the preceding amplifier stage, to this end having a source of constant current connected to its input connection.
摘要翻译：对于运算放大器，电平移位器电路在与其电平移位器功能相关联的前一放大器级上不施加电流负载。公共集电极放大器第一晶体管具有与电平移位器的输入和输出端子的基极和发射极连接。类似导电类型和共集电极正向电流增益的第二晶体管的基极通过第一电流镜放大器连接到电平移位器的输入端，并且其发射极通过第二电流镜放大器连接到输出端电平转换器。第一和第二电流镜放大器具有类似的电流增益。第一电流镜放大器也可以并入用于向前一放大器级提供恒定电流负载的装置中，为此，其具有连接到其输入连接的恒定电流源。

2. 发明授权

US4442409A Push-pull non-complementary transistor amplifier 失效
标题翻译：推挽非互补晶体管放大器
公开(公告)号：US4442409A
公开(公告)日：1984-04-10
申请号：US352179
申请日：1982-02-25
申请人： Donald R. Preslar
发明人： Donald R. Preslar
IPC分类号： H03F3/30
CPC分类号： H03F3/3096
摘要： A push-pull amplifier having like conductivity output transistors is driven by a phase-splitter transistor amplifier. The collector load of the phase-splitter includes a diode bridge for establishing the amplifier idling current. One arm of the bridge incorporates the pull-up output transistor base-emitter junction-the current conducted therein being accurately determined by bridge parameters.
摘要翻译：具有类似导电输出晶体管的推挽放大器由分相器晶体管放大器驱动。分相器的集电极负载包括用于建立放大器空转电流的二极管桥。桥的一个臂结合了上拉输出晶体管基极 - 发射极结，其中传导的电流由桥参数精确地确定。

3. 发明授权

US06919758B1 Controller for FET pass device 有权
标题翻译： FET通过器件控制器
公开(公告)号：US06919758B1
公开(公告)日：2005-07-19
申请号：US10721624
申请日：2003-11-25
申请人： Donald R. Preslar , Thomas J. Hayes
发明人： Donald R. Preslar , Thomas J. Hayes
IPC分类号： G05F1/10 , G05F1/575
CPC分类号： G05F1/575
摘要： A controller for regulating a FET to operate as a pass device including input, output and gate nodes coupled to a current path input, a current path output and the gate of the FET, respectively, a controlled low current device, and an oscillating high gain regulation amplifier. The voltage source provides a regulation voltage level relative to the input node. The low current device is coupled to the gate node and has a control input. The amplifier has a first input coupled to the output node, a second input coupled to the voltage source, and an output coupled to the control input of the controlled low current device to regulate the FET. The amplifier oscillates while regulating a voltage between the input and output nodes to the regulation voltage level. The controlled low current device presents a high impedance to the gate node to prevent oscillations from disturbing regulation.
摘要翻译：一种用于调节FET作为通过装置的控制器，其包括分别耦合到电流路径输入，电流路径输出和FET的栅极的输入，输出和栅极节点，受控低电流装置和振荡高增益调节放大器。电压源提供相对于输入节点的调节电压电平。低电流器件耦合到栅极节点并具有控制输入。放大器具有耦合到输出节点的第一输入端，耦合到电压源的第二输入端和耦合到受控低电流器件的控制输入的输出端以调节FET。放大器在将输入和输出节点之间的电压调节到调节电压电平的同时振荡。受控的低电流器件对栅极节点呈现高阻抗，以防止振荡干扰调节。

4. 发明授权

US6069502A Sample-and-hold circuit having reduced subthreshold conduction effects and related methods 失效
标题翻译：采样保持电路具有降低的亚阈值传导效应和相关方法
公开(公告)号：US6069502A
公开(公告)日：2000-05-30
申请号：US55528
申请日：1998-04-06
申请人： Donald R. Preslar , Salomon Vulih
发明人： Donald R. Preslar , Salomon Vulih
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor. A unity gain buffer amplifier may be connected to the body of the first FET during the holding time for applying a holding voltage from the sampling capacitor to the body to thereby reduce undesired effects from the parasitic diode. The subthreshold current conduction compensation circuit causes a voltage at the first conduction terminal of the first FET to be substantially equal to a voltage at the second conduction terminal of the first FET during the holding time. This may be accomplished by coupling the holding voltage from the output of the buffer amplifier to the node between two series connected FETs.
摘要翻译：集成的采样和保持S / H电路包括用于在保持时间期间减少第一场效应晶体管（FET）中的亚阈值导通电流的不期望的影响的亚阈值传导电流补偿电路。更具体地，S / H电路可以包括衬底，形成在衬底上的采样电容器和第一FET。第一FET具有用于接收输入信号的第一导通端子，连接到采样电容器的第二导通端子和控制端子。控制端子响应于在采样时间期间将输入信号连接到采样电容器的控制信号，以及在保持时间期间从采样电容器断开输入信号。第一FET优选地还包括不幸地产生连接到采样电容器的寄生二极管的主体。在保持时间期间，可以将单位增益缓冲放大器连接到第一FET的主体，以将来自采样电容器的保持电压施加到主体，从而减少来自寄生二极管的不期望的影响。亚阈值电流导通补偿电路使得第一FET的第一导通端子处的电压在保持时间期间基本上等于第一FET的第二导通端子处的电压。这可以通过将保持电压从缓冲放大器的输出耦合到两个串联连接的FET之间的节点来实现。

5. 发明授权

US6002277A Sample-and-hold circuit having reduced parasitic diode effects and related methods 失效
标题翻译：采样保持电路具有减小的寄生二极管效应和相关方法
公开(公告)号：US6002277A
公开(公告)日：1999-12-14
申请号：US55561
申请日：1998-04-06
申请人： Salomon Vulih , Donald R. Preslar , Thomas A. Jochum
发明人： Salomon Vulih , Donald R. Preslar , Thomas A. Jochum
IPC分类号： G11C27/02 , H03K17/00
CPC分类号： G11C27/026
摘要： An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET. The holding voltage overcomes the voltage droop as would otherwise be caused by the parasitic diode. The switches may also connect the body of the first FET to a supply voltage during the sampling time. In addition, the buffer amplifier may have a substantially unity gain.
摘要翻译：集成S / H电路包括形成在具有采样电容器的衬底上的第一场效应晶体管（FET）和具有连接到采样电容器的输入端的缓冲放大器和可连接到第一FET的本体的输出。因此，缓冲放大器减少了由主体和采样电容器形成的寄生二极管的不期望的影响。更具体地，第一FET优选地具有用于接收输入信号的第一导通端子，连接到采样电容器的第二导通端子和响应于在采样时间期间将输入信号连接到采样电容器的控制信号的控制端子，并且用于在保持时间期间从采样电容器断开输入信号。电路可以包括用于在保持时间期间将第一FET的主体连接到缓冲放大器的输出的一个或多个开关，从而将采样电容器的保持电压施加到第一FET的主体。保持电压克服了否则将由寄生二极管引起的电压下降。开关还可以在采样时间期间将第一FET的主体连接到电源电压。此外，缓冲放大器可以具有基本上单位增益。

6. 发明授权

US4322643A Digital phase comparator with improved sensitivity for small phase differences 失效
标题翻译：数字相位比较器，具有改善的小相位差的灵敏度
公开(公告)号：US4322643A
公开(公告)日：1982-03-30
申请号：US144053
申请日：1980-04-28
申请人： Donald R. Preslar
发明人： Donald R. Preslar
IPC分类号： H03K7/08 , H03D13/00 , H03K5/26 , H03L7/089 , H03L7/183
CPC分类号： H03D13/004 , H03L7/0891 , H03L7/0895 , H03L7/183
摘要： A digital phase comparator for essentially eliminating the dead zone in the phase correction means of a phase locked loop. The digital phase comparator is arranged to provide respective up and down output pulses to operate respective charge pumps. The up and down output pulses at all times are greater than a predetermined time duration no matter how small the phase difference between comparator input signals. A delay means is provided in the phase comparator logic, which delay means substantially determines such predetermined time duration. The minimum pulse duration of the up and down signals is selected to be at least of a duration sufficient to operate its respective charge pump, thereby overcoming the finite turn on time of the respective charge pump, no matter how small the phase error.
摘要翻译：数字相位比较器，用于基本消除锁相环相位校正装置中的死区。数字相位比较器布置成提供各自的上下输出脉冲以操作相应的电荷泵。无论比较器输入信号之间的相位差有多小，所有时间的上下输出脉冲均大于预定的持续时间。在相位比较器逻辑中提供延迟装置，该延迟装置基本上确定这样的预定持续时间。上升和下降信号的最小脉冲持续时间被选择为至少足以操作其相应电荷泵的持续时间，从而克服相应电荷泵的有限导通时间，而不管相位误差有多小。

7. 发明授权

US07518430B2 Mechanism for providing over-voltage protection during power up of DC-DC converter 有权
标题翻译：在DC-DC转换器上电期间提供过电压保护的机制
公开(公告)号：US07518430B2
公开(公告)日：2009-04-14
申请号：US11091843
申请日：2005-03-28
申请人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
发明人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
IPC分类号： H03K17/16
CPC分类号： H02M1/36 , H02M1/32 , H02M3/156 , H02M3/1588 , Y02B70/1466
摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
摘要翻译：过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况初始启动系统。响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。

8. 发明授权

US07088151B1 High voltage gate driver using a low voltage multi-level current pulse translator 有权
标题翻译：高压栅极驱动器采用低电压多电平电流脉冲转换器
公开(公告)号：US07088151B1
公开(公告)日：2006-08-08
申请号：US10828610
申请日：2004-04-21
申请人： Noel B. Dequina , Robert H. Isham , Paul K. Sferrazza , Donald R. Preslar
发明人： Noel B. Dequina , Robert H. Isham , Paul K. Sferrazza , Donald R. Preslar
IPC分类号： H03B1/00
CPC分类号： H03K5/08 , H03K5/2472 , H03K17/6871 , H03K17/6872
摘要： A multi-level current pulse generator for driving the gates of a CMOS pair implemented using a low voltage process including a multi-level pulse translator, a current amplifier circuit, and a clamp circuit. The multi-level pulse translator generates a multi-level current pulse on at least one pulse node, each current pulse having a first large current pulse with short duration followed by at least one smaller current pulse of longer duration and operative to switch the CMOS pair with reduced average power dissipation. The current amplifier circuit amplifies the current pulses provided to the gates of the CMOS pair. The clamp circuit clamps gate voltage of the CMOS pair to prevent breakdown. In a tri-level case, a first current pulse charges and discharges gate capacitance, a second current pulse stabilizes gate voltage, and a third current pulse provides a holding current level.
摘要翻译：一种用于驱动使用包括多电平脉冲转换器，电流放大器电路和钳位电路的低电压工艺实现的CMOS对的栅极的多电平电流脉冲发生器。多电平脉冲转换器在至少一个脉冲节点上产生多电平电流脉冲，每个电流脉冲具有短持续时间的第一大电流脉冲，随后是至少一个较长持续时间的较小电流脉冲，并可操作以切换CMOS对降低平均功耗。电流放大器电路放大提供给CMOS对的栅极的电流脉冲。钳位电路钳位CMOS对的栅极电压以防止击穿。在三级情况下，第一电流脉冲对栅极电容进行放电，第二电流脉冲稳定栅极电压，并且第三电流脉冲提供保持电流电平。

9. 发明授权

US6016067A Sample-and-hold circuit having reduced amplifier offset effects and related methods 失效
标题翻译：采样保持电路具有降低的放大器偏移效应和相关方法
公开(公告)号：US6016067A
公开(公告)日：2000-01-18
申请号：US55562
申请日：1998-04-06
申请人： Salomon Vulih , Donald R. Preslar , Thomas A. Jochum
发明人： Salomon Vulih , Donald R. Preslar , Thomas A. Jochum
IPC分类号： G11C27/02 , H03K17/00
CPC分类号： G11C27/026
摘要： An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time. The first FET may further include a body creating a parasitic diode-connected to the first sampling capacitor. To address this parasitic diode, the circuit includes the buffer amplifier having an input connected to the first sampling capacitor and an output connected to the body of the first FET during the holding time. The offset of the buffer amplifier is compensated.
摘要翻译：集成电路采样保持（S / H）电路包括用于补偿缓冲放大器的直流偏移的放大器偏移补偿电路。放大器偏移补偿电路可以包括用于确定由缓冲放大器产生的偏移电压的偏移确定电路和用于产生偏移校正信号并将偏移校正信号耦合到缓冲放大器的偏移校正电路。 S / H电路可以包括衬底，形成在衬底上的采样电容器和形成在衬底上的第一场效应晶体管（FET）。第一FET可以具有用于接收输入信号的第一导电端子，连接到采样电容器的第二导电端子，以及响应于在采样时间期间将输入信号连接到第一采样电容器的控制信号并且用于断开在保持时间期间来自第一采样电容器的输入信号。第一FET还可以包括产生连接到第一采样电容器的寄生二极管的主体。为了寻址这个寄生二极管，电路包括缓冲放大器，其具有连接到第一采样电容器的输入端和在保持时间期间连接到第一FET体的输出端。补偿缓冲放大器的偏移。

10. 发明授权

US5900643A Integrated circuit chip structure for improved packaging 失效
标题翻译：集成电路芯片结构，改进包装
公开(公告)号：US5900643A
公开(公告)日：1999-05-04
申请号：US858845
申请日：1997-05-19
申请人： Donald R. Preslar , John C. Hale
发明人： Donald R. Preslar , John C. Hale
IPC分类号： H01L21/60 , H01L23/485 , H01L23/58 , H01L23/48 , H01L23/52
CPC分类号： H01L23/62 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/49113 , H01L2924/01004 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12035 , H01L2924/14
摘要： First and second electrical components on an integrated circuit chip are electrically connected respectively to a wire bonding pad and to a probe contacting area of a size significantly less than the bonding pad. The pad and contacting area are electrically isolated whereby both components can be separately electrically tested by test probes contacting each of the pad and the contact area. After the components have been tested, the bonding pad and the probe contact area are electrically connected together for electrically connecting the first and second components. The electrical connection is made by bonding a terminal wire to the bonding pad as well as to an extension from the contact area substantially filling a space within the bonding pad and underlying the joint formed between the terminal wire and the bonding pad.
摘要翻译：集成电路芯片上的第一和第二电气部件分别电连接到引线接合焊盘和尺寸明显小于接合焊盘的探针接触区域。焊盘和接触区域是电隔离的，由此两个部件可以通过接触焊盘和接触区域的每个的测试探针分开地电测试。在已经测试了部件之后，焊盘和探针接触区域电连接在一起，以电连接第一和第二部件。电连接是通过将端子线接合到接合焊盘以及从基本上填充接合焊盘内的空间并且形成在端子线和接合焊盘之间的接头下方的接触区域延伸而形成的。

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