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1. 发明授权

US06873191B2 Mechanism for providing over-voltage protection during power up of DC-DC converter 有权
标题翻译：在DC-DC转换器上电期间提供过电压保护的机制
公开(公告)号：US06873191B2
公开(公告)日：2005-03-29
申请号：US10685314
申请日：2003-10-14
申请人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
发明人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
IPC分类号： H02M1/00 , H02M1/36 , H02M3/156 , H02M3/158 , H03K3/00
CPC分类号： H02M1/36 , H02M1/32 , H02M3/156 , H02M3/1588 , Y02B70/1466
摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC—DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
摘要翻译：过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况初始启动系统。响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。

2. 发明授权

US07518430B2 Mechanism for providing over-voltage protection during power up of DC-DC converter 有权
标题翻译：在DC-DC转换器上电期间提供过电压保护的机制
公开(公告)号：US07518430B2
公开(公告)日：2009-04-14
申请号：US11091843
申请日：2005-03-28
申请人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
发明人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
IPC分类号： H03K17/16
CPC分类号： H02M1/36 , H02M1/32 , H02M3/156 , H02M3/1588 , Y02B70/1466
摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
摘要翻译：过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况初始启动系统。响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。

3. 发明授权

US07088151B1 High voltage gate driver using a low voltage multi-level current pulse translator 有权
标题翻译：高压栅极驱动器采用低电压多电平电流脉冲转换器
公开(公告)号：US07088151B1
公开(公告)日：2006-08-08
申请号：US10828610
申请日：2004-04-21
申请人： Noel B. Dequina , Robert H. Isham , Paul K. Sferrazza , Donald R. Preslar
发明人： Noel B. Dequina , Robert H. Isham , Paul K. Sferrazza , Donald R. Preslar
IPC分类号： H03B1/00
CPC分类号： H03K5/08 , H03K5/2472 , H03K17/6871 , H03K17/6872
摘要： A multi-level current pulse generator for driving the gates of a CMOS pair implemented using a low voltage process including a multi-level pulse translator, a current amplifier circuit, and a clamp circuit. The multi-level pulse translator generates a multi-level current pulse on at least one pulse node, each current pulse having a first large current pulse with short duration followed by at least one smaller current pulse of longer duration and operative to switch the CMOS pair with reduced average power dissipation. The current amplifier circuit amplifies the current pulses provided to the gates of the CMOS pair. The clamp circuit clamps gate voltage of the CMOS pair to prevent breakdown. In a tri-level case, a first current pulse charges and discharges gate capacitance, a second current pulse stabilizes gate voltage, and a third current pulse provides a holding current level.
摘要翻译：一种用于驱动使用包括多电平脉冲转换器，电流放大器电路和钳位电路的低电压工艺实现的CMOS对的栅极的多电平电流脉冲发生器。多电平脉冲转换器在至少一个脉冲节点上产生多电平电流脉冲，每个电流脉冲具有短持续时间的第一大电流脉冲，随后是至少一个较长持续时间的较小电流脉冲，并可操作以切换CMOS对降低平均功耗。电流放大器电路放大提供给CMOS对的栅极的电流脉冲。钳位电路钳位CMOS对的栅极电压以防止击穿。在三级情况下，第一电流脉冲对栅极电容进行放电，第二电流脉冲稳定栅极电压，并且第三电流脉冲提供保持电流电平。

4. 发明授权

US07031175B2 System and method of detecting phase body diode using a comparator in a synchronous rectified FET driver 有权
标题翻译：在同步整流FET驱动器中使用比较器检测相体二极管的系统和方法
公开(公告)号：US07031175B2
公开(公告)日：2006-04-18
申请号：US10797437
申请日：2004-03-10
申请人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
发明人： Noel B. Dequina , Donald R. Preslar , Paul K. Sferrazza
IPC分类号： H02M7/217
CPC分类号： H02M1/088 , H02M1/38 , H02M3/1588 , H03K17/0822 , H03K17/6871 , Y02B70/1466
摘要： A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.
摘要翻译：一种用于包括采样电路和比较器的同步整流FET驱动器的体二极管比较器电路。 FET驱动器具有耦合在一对上开关FET和下开关FET之间的相位节点，并且响应于具有用于每个周期的第一和第二相的PWM信号。采样电路在PWM信号的第一阶段期间对相位节点的初始电压进行采样，并且在PWM信号的第二阶段期间提供指示相位节点的初始相位电压的和电压。比较器将和电压与预定参考电压进行比较，并在PWM信号的第二阶段期间提供指示下FET的激活状态的输出。当比较器指示下部FET关闭时，FET驱动器接通上部FET。

5. 发明申请

US20090027024A1 LOAD CURRENT COMPENSATION IN SYNCHRONOUS POWER CONVERTERS 有权
标题翻译：同步电源转换器中的负载电流补偿
公开(公告)号：US20090027024A1
公开(公告)日：2009-01-29
申请号：US12176759
申请日：2008-07-21
申请人： Noel B. Dequina
发明人： Noel B. Dequina
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , H02M1/38 , Y02B70/1466
摘要： A method of operating a synchronous power converter generates a control signal in a load current compensation circuit based on a light load condition at the converter, where the control signal controls a gate driver for at least one power switch of the converter. When the gate driver is turned off via the control signal, the method monitors one or more comparison signals in a reference voltage adjustment module of the compensation circuit, a first comparison signal of the one or more comparison signals indicative of a voltage level at a phase node of the converter. Based on a remaining body diode conduction level associated a body diode with the at least one power switch as detected by at least a second comparison signal, the method adjusts a reference voltage for the at least one power switch with the adjustment module until the body diode is no longer conducting.
摘要翻译：一种操作同步功率转换器的方法基于转换器上的轻负载条件在负载电流补偿电路中产生控制信号，其中控制信号控制转换器的至少一个电源开关的栅极驱动器。当通过控制信号关闭栅极驱动器时，该方法监视补偿电路的参考电压调节模块中的一个或多个比较信号，该一个或多个比较信号的第一比较信号指示相位处的电压电平节点的转换器。基于通过至少第二比较信号检测到的体二极管与至少一个功率开关相关联的剩余体二极管导通电平，该方法利用调节模块调整至少一个功率开关的参考电压，直到体二极管不再进行。

6. 发明授权

US08203359B2 System and method for open loop modulation to detect narrow PWM pulse 有权
标题翻译：用于开环调制的系统和方法，用于检测窄脉宽
公开(公告)号：US08203359B2
公开(公告)日：2012-06-19
申请号：US13034416
申请日：2011-02-24
申请人： Noel B. Dequina , M. Jason Houston
发明人： Noel B. Dequina , M. Jason Houston
IPC分类号： H03K19/0175
CPC分类号： H02M3/158 , H02M3/156 , H02M2001/0003
摘要： An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal.
摘要翻译：一种用于电压调节器的开环调制网络，包括锁存网络，输出检测网络，定时网络和脉冲控制逻辑。锁存网络锁存脉冲控制信号的断言并提供对应的锁存控制脉冲指示。输出检测网络检测输出脉冲的启动并提供相应的输出脉冲指示。定时网络响应于输出脉冲指示启动延迟时段，并且在延迟时间期满之后复位锁存的控制脉冲指示。在锁存的控制脉冲指示被复位并且脉冲控制信号被否定之后，脉冲控制逻辑终止输出脉冲，以最后发生者为准。检测到非常窄的输入脉冲，并且产生最小输出脉冲，或者输出脉冲基于脉冲控制信号。

7. 发明授权

US07868597B2 Dead-time transition adjustments for synchronous power converters 失效
标题翻译：同步电源转换器的死区转换调整
公开(公告)号：US07868597B2
公开(公告)日：2011-01-11
申请号：US12176762
申请日：2008-07-21
申请人： Noel B. Dequina
发明人： Noel B. Dequina
IPC分类号： G05F1/652 , G05F1/613
CPC分类号： H02M3/1588 , H02M1/38 , Y02B70/1466
摘要： A method of operating a synchronous power converter detects when at least one of an upper power switch and a lower power switch of the converter transition to an off state during a dead-time transition interval between the upper power switch and the lower power switch. The method generates a first comparison signal, indicative of a voltage level at a phase node of the converter, in a dead-time adjustment circuit coupled to the converter. The method further detects a body diode conduction level of at least one of the upper and lower power switches in the off state using at least a second comparison signal generated in the dead-time adjustment circuit and adjusts the dead-time transition interval between the upper power switch and the lower power switch using at least one current source from the dead-time adjustment circuit to reduce the dead-time transition interval to a desired dead-time interval.
摘要翻译：操作同步功率转换器的方法检测在上电源开关和下电源开关之间的死区时间过渡间隔期间，转换器的上电源开关和下电源开关中的至少一个转换到断开状态。该方法在耦合到转换器的死区时间调整电路中产生指示转换器的相位节点处的电压电平的第一比较信号。该方法还使用在死区时间调整电路中产生的至少第二比较信号，检测处于断开状态的上下功率开关中的至少一个的体二极管导通电平，并且调节上限和下限功率开关之间的死区时间过渡间隔电源开关和下电源开关，其使用来自死区时间调整电路的至少一个电流源，以将死区时间转换间隔减少到期望的死区间隔。

8. 发明授权

US07514992B2 Circuit for generating precision soft-start frequency for either value of address bit applied to external reset pin 有权
标题翻译：用于产生精确软启动频率的电路，用于施加到外部复位引脚的地址位的任一值
公开(公告)号：US07514992B2
公开(公告)日：2009-04-07
申请号：US11358609
申请日：2006-02-21
申请人： Noel B. Dequina , Robert Haynes Isham
发明人： Noel B. Dequina , Robert Haynes Isham
IPC分类号： H03K17/687
CPC分类号： H03K19/1732 , H02M1/36
摘要： A multi-function circuit has as single input/control pin, to which respectively different values of a control input may be applied. A multi-function signal generation section is coupled to the single input/control pin and is operative to controllably generate a plurality of respectively different functional outputs, including a decoded address bit-representative output, a soft-start oscillator signal output, and a reset output, in response to application of respectively different values of the control input.
摘要翻译：多功能电路具有作为单个输入/控制引脚，可以分别应用控制输入的不同值。多功能信号产生部分耦合到单个输入/控制引脚，并且可操作地可控地产生多个分别不同的功能输出，包括解码地址位代表输出，软启动振荡器信号输出和复位输出，响应于应用分别不同的控制输入值。

9. 发明授权

US08299770B2 Threshold voltage monitoring and control in synchronous power converters 有权
标题翻译：同步电源转换器的阈值电压监控与控制
公开(公告)号：US08299770B2
公开(公告)日：2012-10-30
申请号：US13047065
申请日：2011-03-14
申请人： Weihong Qiu , Noel B. Dequina
发明人： Weihong Qiu , Noel B. Dequina
IPC分类号： G05F1/613 , G05F1/656
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A method of providing threshold voltage monitoring and control in synchronous power converters is provided. The method includes establishing a threshold voltage level for at least one of a gate drive voltage for an upper and a lower power switch in a synchronous power converter, each threshold voltage level controlling a switching delay time for one of the upper and lower power switches. The method further includes detecting body diode conduction levels for at least one of the upper and lower power switches and adjusting the threshold voltage level for at least one of the upper and lower power switches, based on the detected body diode conduction levels, to fine-tune a body diode conduction time around an equilibrium for the at least one of the upper and lower power switches.
摘要翻译：提供了一种在同步电源转换器中提供阈值电压监测和控制的方法。该方法包括为同步功率转换器中的上电源开关和下电源开关的栅极驱动电压中的至少一个建立阈值电压电平，每个阈值电压电平控制上电源开关和下电源开关之一的开关延迟时间。该方法还包括检测上部和下部功率开关中的至少一个的体二极管导通电平，并且基于检测到的体二极管导通电平调整上和下功率开关中的至少一个的阈值电压电平，调谐体二极管导通时间，围绕上下电源开关中的至少一个的平衡。

10. 发明申请

US20110163731A1 THRESHOLD VOLTAGE MONITORING AND CONTROL IN SYNCHRONOUS POWER CONVERTERS 有权
标题翻译：同步电源转换器的阈值电压监控与控制
公开(公告)号：US20110163731A1
公开(公告)日：2011-07-07
申请号：US13047065
申请日：2011-03-14
申请人： Weihong Qiu , Noel B. Dequina
发明人： Weihong Qiu , Noel B. Dequina
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A method of providing threshold voltage monitoring and control in synchronous power converters is provided. The method includes establishing a threshold voltage level for at least one of a gate drive voltage for an upper and a lower power switch in a synchronous power converter, each threshold voltage level controlling a switching delay time for one of the upper and lower power switches. The method further includes detecting body diode conduction levels for at least one of the upper and lower power switches and adjusting the threshold voltage level for at least one of the upper and lower power switches, based on the detected body diode conduction levels, to fine-tune a body diode conduction time around an equilibrium for the at least one of the upper and lower power switches.
摘要翻译：提供了一种在同步电源转换器中提供阈值电压监测和控制的方法。该方法包括为同步功率转换器中的上电源开关和下电源开关的栅极驱动电压中的至少一个建立阈值电压电平，每个阈值电压电平控制上电源开关和下电源开关之一的开关延迟时间。该方法还包括检测上部和下部功率开关中的至少一个的体二极管导通电平，并且基于检测到的体二极管导通电平调整上和下功率开关中的至少一个的阈值电压电平，调谐体二极管导通时间，围绕上下电源开关中的至少一个的平衡。

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