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1. 发明授权

US07777656B2 Decoding, encoding/decoding and converting 有权
标题翻译：解码，编码/解码和转换
公开(公告)号：US07777656B2
公开(公告)日：2010-08-17
申请号：US11749191
申请日：2007-05-16
申请人： Luis Hernandez , Dietmar Straeussnigg , Andreas Wiesbauer
发明人： Luis Hernandez , Dietmar Straeussnigg , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03M1/504 , H03M1/822
摘要： Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.
摘要翻译：描述和描述了解码器，编码器/解码器系统和转换器的实现和实施例。

2. 发明申请

US20110268173A1 METHOD FOR ADAPTING FILTER CUT-OFF FREQUENCIES FOR THE TRANSMISSION OF DISCRETE MULTITONE SYMBOLS 审中-公开
标题翻译：用于传送离散多重符号的滤波器切断频率的方法
公开(公告)号：US20110268173A1
公开(公告)日：2011-11-03
申请号：US13173616
申请日：2011-06-30
申请人： Dietmar Straeussnigg
发明人： Dietmar Straeussnigg
IPC分类号： H04L27/01
CPC分类号： H04L27/2647 , H04L25/03834 , H04L27/2607 , H04L27/2644 , H04L27/3405
摘要： The invention creates a method for adapting filter cut-off frequencies for the transmission of discrete multitone symbols, where a transmit symbol datastream consisting of discrete multitone symbols is applied to an interpolation device, the transmit symbol datastream is interpolated with a symbol rate in the interpolation device, an interpolated symbol datastream is filtered in a first low-pass filtering device in accordance with a first filter cut-off frequency, which can be predetermined by a first filter cut-off frequency determining device, a digital symbol datastream obtained after a digital-analog conversion, transmission and analog-digital conversion, is filtered at the receiver end in a second low-pass filtering device in accordance with a second filter cut-off frequency, which can be predetermined by a second filter cut-off frequency determining device, in order to provide an equalized symbol datastream, the equalized symbol datastream is decimated in a decimation device and the decimated received symbol datastream consisting of discrete multitone symbols is provided to a multitone receiver device.
摘要翻译：本发明创建了一种用于适配用于离散多音符号的传输的滤波器截止频率的方法，其中由离散多音符号组成的发射符号数据流被应用于内插装置，在插值中以符号率内插发送符号数据流内插符号数据流根据第一滤波器截止频率在第一低通滤波装置中被滤波，该第一滤波器截止频率可由第一滤波器截止频率确定装置预定，数字符号数据流在数字根据第二滤波器截止频率，在第二低通滤波装置的接收端处滤波 - 传输和模数转换，其可以由第二滤波器截止频率确定装置为了提供均衡的符号数据流，在抽取装置中抽取均衡的符号数据流将由离散多音符号组成的抽取的接收符号数据流提供给多音调接收机设备。

3. 发明申请

US20110115453A1 NONLINEAR CONTROL LOOP FOR DC-DC CONVERTERS 有权
标题翻译： DC-DC转换器的非线性控制环路
公开(公告)号：US20110115453A1
公开(公告)日：2011-05-19
申请号：US12620076
申请日：2009-11-17
申请人： Stefano Marsili , Dietmar Straeussnigg , Luca Bizjak , Robert Priewasser , Matteo Agostinelli
发明人： Stefano Marsili , Dietmar Straeussnigg , Luca Bizjak , Robert Priewasser , Matteo Agostinelli
IPC分类号： G05F1/00 , G05F1/10
CPC分类号： H02M3/1582 , H02M2001/0003
摘要： A nonlinear converter, such as a DC-DC converter, includes a nonlinear controller configured to receive an output voltage and a current, and configured to generate a PWM signal. The PWM signal is generated based on setting the converter to a first phase associated with both buck and boost modes when a clock signal is asserted, and selecting a second phase associated with the buck mode of the converter, if a sliding function signal achieves a first predetermined relationship with respect to a buck threshold before a next clock signal is asserted, or selecting a third phase associated with the boost mode of the converter, if the sliding function signal achieves a second predetermined relationship with respect to a boost threshold before a next clock signal is asserted. The nonlinear converter may include a power stage configured to provide the output voltage and a coil current to the nonlinear controller.
摘要翻译：诸如DC-DC转换器的非线性转换器包括被配置为接收输出电压和电流并被配置为产生PWM信号的非线性控制器。如果滑动功能信号达到第一个状态，则基于将时钟信号置位时，将转换器设置为与降压模式和升压模式相关联的第一相位，以及选择与转换器的降压模式相关联的第二相位来生成PWM信号如果滑动功能信号在下一个时钟之前达到相对于升压阈值的第二预定关系，则相关于下一个时钟信号被断言之前的降压阈值的预定关系，或者选择与转换器的升压模式相关联的第三相位信号被断言。非线性转换器可以包括被配置为向非线性控制器提供输出电压和线圈电流的功率级。

4. 发明申请

US20110050475A1 ANALOG TO DIGITAL CONVERTER WITH DIGITAL FILTER 有权
标题翻译：模拟数字转换器与数字滤波器
公开(公告)号：US20110050475A1
公开(公告)日：2011-03-03
申请号：US12551337
申请日：2009-08-31
申请人： Dietmar Straeussnigg , Andreas Wiesbauer
发明人： Dietmar Straeussnigg , Andreas Wiesbauer
IPC分类号： H03M1/12
CPC分类号： H03M3/412
摘要： Disclosed herein are devices, methods, and techniques including analog to digital converters having at least one digital filter.
摘要翻译：本文公开了包括具有至少一个数字滤波器的模数转换器的装置，方法和技术。

5. 发明授权

US08411871B2 Echo cancellation 有权
公开(公告)号：US08411871B2
公开(公告)日：2013-04-02
申请号：US11842964
申请日：2007-08-22
申请人： David Schwingshackl , Joerg Hauptmann , Gerhard Paoli , Dietmar Straeussnigg
发明人： David Schwingshackl , Joerg Hauptmann , Gerhard Paoli , Dietmar Straeussnigg
IPC分类号： H04B3/20
CPC分类号： H04B3/237
摘要： Implementations related to echo cancellation are depicted and described herein.

6. 发明申请

US20100213999A1 Dynamic Element Matchinig for Delay Lines 有权
标题翻译：用于延迟线的动态元素匹配
公开(公告)号：US20100213999A1
公开(公告)日：2010-08-26
申请号：US12392046
申请日：2009-02-24
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straeussnigg
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straeussnigg
IPC分类号： H03H11/26
CPC分类号： H03M1/066 , G04F10/005 , H03M1/502
摘要： This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.
摘要翻译：本公开涉及延迟线电路中的动态元件匹配以减少线性劣化和延迟线不匹配。

7. 发明授权

US07629916B2 Multiple output time-to-digital converter 有权
标题翻译：多输出时间 - 数字转换器
公开(公告)号：US07629916B2
公开(公告)日：2009-12-08
申请号：US12062538
申请日：2008-04-04
申请人： Andreas Wiesbauer , Luis Hernandez , Wim Dehaene , Jorg Daniels , Dietmar Straeussnigg
发明人： Andreas Wiesbauer , Luis Hernandez , Wim Dehaene , Jorg Daniels , Dietmar Straeussnigg
IPC分类号： H03M1/50
CPC分类号： H03M3/428 , G04F10/005 , H03M3/456
摘要： A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.
摘要翻译：公开了一种多输出时间数字转换器（TDC）和并入多输出TDC的模数转换器（ADC）。

8. 发明授权

US07123661B2 Datastream transmitters for discrete multitone systems 有权
公开(公告)号：US07123661B2
公开(公告)日：2006-10-17
申请号：US10175504
申请日：2002-06-19
申请人： Dietmar Straeussnigg
发明人： Dietmar Straeussnigg
IPC分类号： H04K1/10
CPC分类号： H04L27/2626 , H04L25/03343
摘要： A method for transmitting an analog datastream includes coding data input into a data input device. The resulting coded data is assembled into coded data blocks. These blocks are transformed into at least one discrete multitone symbol. An initial filter value extracted from the discrete multitone symbol is forwarded to a stored-value determining device, to which a frame alignment signal has been applied. A stored value for a first filtering device is determined as a function of the at least one initial filter value and the frame alignment signal. This value, and the multitone symbol, are applied to the first filtering device, thereby generating a filtered discrete multitone symbol. The filtered symbol is forwarded to a second filtering device to which the stored value determined in the stored-value determining device is applied, thereby generating a transient-compensated discrete multitone symbol. This is then converted into an analog signal for transmission.

9. 发明授权

US07012979B2 Tone signal detection circuit for detecting tone signals 有权
标题翻译：用于检测音调信号的音频信号检测电路
公开(公告)号：US07012979B2
公开(公告)日：2006-03-14
申请号：US09942518
申请日：2001-08-29
申请人： Jörg Hauptmann , Thomas Pötscher , Michael Staber , Dietmar Straeussnigg , Hubert Weinberger
发明人： Jörg Hauptmann , Thomas Pötscher , Michael Staber , Dietmar Straeussnigg , Hubert Weinberger
IPC分类号： H04L7/00
CPC分类号： H04L27/1563 , H04L2027/0083
摘要： Tone signal detection circuit for a receiving circuit for detecting at least one tone signal of predetermined tone signal frequency (fE) which is contained in a received analog input signal, comprising a reference signal generator (41) for generating an analog converter reference signal which consists of a reference DC (VrefDC) and a periodic reference AC (VrefAC) having a variable fundamental frequency (fG), which is superimposed on the reference DC, an analog/digital converter (11) for converting the analog input signal into a digital data stream in dependence on the analog converter reference signal (Vref); and comprising a digital control circuit (20) which adjusts the variable fundamental frequency (fG) of the reference signal (Vref) generated by the reference signal generator (42) in accordance with the predetermined tone signal frequencies (fG) of the tone signals to be detected and evaluates the digital data stream output by the digital analog/digital converter (11) for detecting a data pattern corresponding to the tone signal.
摘要翻译：一种用于检测包含在接收的模拟输入信号中的预定音调信号频率（f SUB）的至少一个音调信号的接收电路的音频信号检测电路，包括：参考信号发生器（41），用于产生一个模拟转换器参考信号，该参考信号由具有可变基频（f SUB）的参考DC（V SUB refDC）和周期性参考AC（V SUB REFAC ），其叠加在参考DC上;模拟/数字转换器（11），用于根据模拟转换器参考信号（V SUB ref ）; 并且包括数字控制电路（20），其调整由参考信号发生器（42）产生的参考信号（V SUB ref）的可变基频（f SUB）根据要检测的音调信号的预定音调信号频率（f SUB）来评估由数字模拟/数字转换器（11）输出的数字数据流，用于检测对应于音调信号。

10. 发明授权

US09520785B2 Nonlinear control loop for DC-DC converters 有权
标题翻译： DC-DC转换器的非线性控制回路
公开(公告)号：US09520785B2
公开(公告)日：2016-12-13
申请号：US12620076
申请日：2009-11-17
申请人： Stefano Marsili , Dietmar Straeussnigg , Luca Bizjak , Robert Priewasser , Matteo Agostinelli
发明人： Stefano Marsili , Dietmar Straeussnigg , Luca Bizjak , Robert Priewasser , Matteo Agostinelli
IPC分类号： H02M3/158 , H02M1/00
CPC分类号： H02M3/1582 , H02M2001/0003
摘要： A nonlinear converter, such as a DC-DC converter, includes a nonlinear controller configured to receive an output voltage and a current, and configured to generate a PWM signal. The PWM signal is generated based on setting the converter to a first phase associated with both buck and boost modes when a clock signal is asserted, and selecting a second phase associated with the buck mode of the converter, if a sliding function signal achieves a first predetermined relationship with respect to a buck threshold before a next clock signal is asserted, or selecting a third phase associated with the boost mode of the converter, if the sliding function signal achieves a second predetermined relationship with respect to a boost threshold before a next clock signal is asserted. The nonlinear converter may include a power stage configured to provide the output voltage and a coil current to the nonlinear controller.
摘要翻译：诸如DC-DC转换器的非线性转换器包括被配置为接收输出电压和电流并被配置为产生PWM信号的非线性控制器。如果滑动功能信号达到第一个状态，则基于将时钟信号置位时，将转换器设置为与降压模式和升压模式相关联的第一相位，以及选择与转换器的降压模式相关联的第二相位来生成PWM信号如果滑动功能信号在下一个时钟之前达到相对于升压阈值的第二预定关系，则相关于下一个时钟信号被断言之前的降压阈值的预定关系，或者选择与转换器的升压模式相关联的第三相位信号被断言。非线性转换器可以包括被配置为向非线性控制器提供输出电压和线圈电流的功率级。

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