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1. 发明授权

US07642865B2 System and method for multiple-phase clock generation 有权
标题翻译：用于多相时钟生成的系统和方法
公开(公告)号：US07642865B2
公开(公告)日：2010-01-05
申请号：US11616742
申请日：2006-12-27
申请人： Tanmoy Sen , Anand Kumar , Deependra Kumar Jain
发明人： Tanmoy Sen , Anand Kumar , Deependra Kumar Jain
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03K3/03 , H03K5/15013 , H03K5/15026 , H03K5/1506 , H03K2005/00241 , H03K2005/00247 , H03L7/095 , H03L7/0995 , Y10S331/02
摘要： A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.
摘要翻译：多相时钟电路包括多级压控振荡器（VCO）和多个时钟分频器。 VCO的工作频率高于所需输出频率的“N”倍，并产生具有不同相位但相同频率的“M”等间距输出，发送到多个时钟分频器。修改后的约翰逊计数器用作时钟分频器。每个计数器将时钟信号的频率除以N.结果，VCO的M个输出中的每一个被分成N个输出，从而形成总共“M×N”个等间隔的输出。这些输出时钟脉冲具有相同的频率但不同的相位。在该装置内提供一个顺序逻辑，用于一旦VCO开始输出输出就能使约翰逊计数器得以实现，从而保持约翰逊计数器的输出顺序。

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