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    • 1. 发明授权
    • Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing
    • 用于跨晶片背压差的方法和装置,以影响化学机械抛光的性能
    • US06531397B1
    • 2003-03-11
    • US09005364
    • 1998-01-09
    • Ronald J. NagaharaDawn M. Lee
    • Ronald J. NagaharaDawn M. Lee
    • H01L21302
    • B24B37/30
    • Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished. In one embodiment, the second mechanism is arranged to apply both positive pressure and negative pressure substantially simultaneously across the second surface of the semiconductor wafer.
    • 公开了通过在晶片的背面施加不均匀的压力分布来平坦化半导体晶片的表面的方法和装置。 根据本发明的一个方面,一种用于抛光半导体晶片的第一表面的化学机械抛光装置包括:抛光衬垫,其抛光半导体晶片的第一表面。 该装置还包括用于在抛光期间保持或以其他方式支撑晶片的第一机构,以及用于将非均匀压力分布通过第一机构施加到第二机构的第二机构,直接施加到晶片的第二表面上 。 第二机构还用于促进对半导体晶片的第一表面进行抛光,使得半导体晶片的第一表面被均匀地抛光。 在一个实施例中,第二机构被布置成在半导体晶片的第二表面上基本上同时施加正压和负压。
    • 4. 发明授权
    • Polishing pad surface for improved process control
    • 抛光垫表面,用于改进过程控制
    • US06168508A
    • 2001-01-02
    • US08918293
    • 1997-08-25
    • Ronald J. NagaharaDawn M. Lee
    • Ronald J. NagaharaDawn M. Lee
    • B24D1100
    • B24B37/24B24B37/26
    • A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.
    • 描述了用于集成电路表面的化学机械抛光的抛光垫。 抛光垫包括具有物理性质的第一值的第一抛光区域; 以及具有所述物理性质的第二值的第二抛光区域,所述第二值不同于第一值,使得在集成电路表面的化学机械抛光期间,集成电路在抛光垫上旋转并振荡,使得 集成电路表面的大部分接触第一和第二抛光区域,其中所述第一和第二抛光区域的宽度大于约40密耳。
    • 5. 发明授权
    • Effective pad conditioning
    • 有效垫调节
    • US6106371A
    • 2000-08-22
    • US961383
    • 1997-10-30
    • Ronald J. NagaharaDawn M. Lee
    • Ronald J. NagaharaDawn M. Lee
    • B24B37/26B24B53/007B24B53/017B24D13/14B24B1/00
    • B24B37/26B24B53/017B24D13/14
    • An end effector to facilitate conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface is described. The end effector includes an inwardly recessing contact surface capable of attaching to a conditioning disk having a conditioning surface such that the conditioning surface conforms to a substantial portion of the polishing pad, which protrudes outwardly under operation and thereby effectively conditions a substantial portion of the polishing pad. The present invention also describes a conditioning disk for effectively conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface. The conditioning disk includes (i) a second surface capable of attaching to a contact surface of an end effector and (ii) an inwardly recessing conditioning surface that conforms to a substantial portion of said polishing pad, which protrudes outwardly under operation, and thereby effectively conditions the polishing pad. Processes and a chemical-mechanical polishing apparatuses employing the inventive end effectors or conditioning disks are also described.
    • 描述了一种端部执行器,以便于调节用于衬底表面的化学机械抛光的抛光垫的表面。 末端执行器包括向内凹入的接触表面,其能够附接到具有调节表面的调节盘,使得调节表面符合抛光垫的大部分,其在操作下向外突出,从而有效地调节抛光的大部分 垫。 本发明还描述了一种用于有效调节用于衬底表面的化学机械抛光的抛光垫的表面的调节盘。 调节盘包括(i)能够附接到端部执行器的接触表面的第二表面和(ii)符合在操作中向外突出的所述抛光垫的大部分的向内凹陷的调节表面,从而有效地 调节抛光垫。 还描述了采用本发明的末端效应器或调节盘的方法和化学机械抛光装置。
    • 8. 发明授权
    • Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
    • 用于CMP去除多余沟槽或通过填充金属的方法,其抑制在集成电路结构的氧化物表面上形成凹陷区域
    • US06391768B1
    • 2002-05-21
    • US09703616
    • 2000-10-30
    • Dawn M. LeeJayanthi PallintiWeidan LiMing-Yi Lee
    • Dawn M. LeeJayanthi PallintiWeidan LiMing-Yi Lee
    • H01L214763
    • H01L21/7684
    • A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer. Trenches and/or vias are formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled by depositing at least one metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a CMP stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process to remove metal, than does the oxide dielectric layer, the formation of dished or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.
    • 公开了一种用于在填充之后通过化学机械抛光(CMP)对集成电路结构进行平面化的工艺,其中至少一个金属,形成在集成电路结构上的氧化硅层中的多个沟槽和/或通孔。 在CMP工艺期间,能够阻止在氧化硅表面上形成凹面部分的工艺,其中所述沟槽和/或通孔紧密间隔开的区域中,包括在集成的 电路结构,能够在CMP工艺中用作去除金属的停止层的介电材料的抗反射涂层(ARC)层; 并且使用该ARC层作为停止层来辅助去除用于填充形成在氧化物层中的沟槽和/或通孔的多余金属。 选择用于ARC层的特定材料在CMP工艺中应该具有比底层氧化物介电层更低的去除金属的蚀刻速率。 通过ARC层和氧化物介电层形成沟槽和/或通孔。 然后通过在ARC层上沉积至少一个金属层来填充这些沟槽和/或通孔。 然后通过对金属进行对ARC层有选择性的CMP步骤,从ARC层的顶表面去除过量的沟槽和/或通孔填充金属,从而允许ARC层用作CMP停止层,其保护 潜在的氧化物介电层暴露于CMP工艺。 由于ARC层具有较低的蚀刻速率,所以在除去金属的CMP工艺中,与氧化物电介质层相比,抑制了表面上的凹陷或凹陷区域的形成,包括沟槽和/或通孔密切的区域 间隔开