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1. 发明授权

US5392224A Midi through port hardware emulator 失效
标题翻译： Midi通过端口硬件仿真器
公开(公告)号：US5392224A
公开(公告)日：1995-02-21
申请号：US91954
申请日：1993-07-14
申请人： Alejandro R. Badia , David P. Pagnani , Edward D. Shockley
发明人： Alejandro R. Badia , David P. Pagnani , Edward D. Shockley
IPC分类号： G06F11/25 , G06F11/26 , G10H1/00 , G06F15/60
CPC分类号： G10H1/0066 , G06F11/25 , G06F11/26
摘要： Disclosed is a Musical Instrument Digital Interface emulator for testing the THRU port echo of a Musical Instrument Digital Interface device. The emulator has input devices for taking bitstream data from the THRU and OUT ports of the Musical Instrument Digital Interface device, comparing the THRU port bitstream data to the OUT port bitstream data, and generating a result of the comparison. Also disclosed is a method of testing the THRU port echo of a Musical Instrument Digital Interface device by reading the THRU bitstream and OUT bitstream of the Musical Digital Interface Device, bitwise comparing the two bit streams; and reporting the results of the comparison to an output means.
摘要翻译：公开了一种用于测试乐器数字接口设备的THRU端口回声的乐器数字接口仿真器。仿真器具有用于从乐器数字接口设备的THRU和OUT端口获取位流数据的输入设备，将THRU端口位流数据与OUT端口位流数据进行比较，并产生比较结果。还公开了一种通过读取音乐数字接口装置的THRU比特流和OUT比特流来比较两个比特流来测试乐器数字接口装置的THRU端口回波的方法; 并将比较结果报告给输出装置。

2. 发明授权

US5028983A Multilevel integrated circuit packaging structures 失效
标题翻译：多层集成电路封装结构
公开(公告)号：US5028983A
公开(公告)日：1991-07-02
申请号：US263835
申请日：1988-10-27
申请人： Harry R. Bickford , Mark F. Bregman , Thomas M. Cipolla , John Gow, III , Peter G. Ledermann , Ekkehard F. Miersch , Leonard T. Olson , David P. Pagnani , Timothy C. Reiley , Uh-Po E. Tsou , Walter V. Vilkelis
发明人： Harry R. Bickford , Mark F. Bregman , Thomas M. Cipolla , John Gow, III , Peter G. Ledermann , Ekkehard F. Miersch , Leonard T. Olson , David P. Pagnani , Timothy C. Reiley , Uh-Po E. Tsou , Walter V. Vilkelis
IPC分类号： H01L21/60 , H01L23/495 , H01L23/498
CPC分类号： H01L24/50 , H01L23/49572 , H01L23/49861 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/3011
摘要： Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

3. 发明授权

US4916259A Composite dielectric structure for optimizing electrical performance in high performance chip support packages 失效
标题翻译：用于优化高性能芯片支持封装中的电气性能的复合介质结构
公开(公告)号：US4916259A
公开(公告)日：1990-04-10
申请号：US375247
申请日：1989-07-03
申请人： Ronald S. Charsky , Leonard T. Olson , David P. Pagnani
发明人： Ronald S. Charsky , Leonard T. Olson , David P. Pagnani
IPC分类号： H01L23/14 , H01L23/64 , H05K1/00 , H05K1/02 , H05K1/03 , H05K3/46
CPC分类号： H05K1/024 , H01L23/14 , H01L23/64 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K2201/0154 , H05K2201/0195 , H05K3/4644 , H05K3/4676 , Y10T428/31623
摘要： The disclosure describes a technique whereby the electrical characteristics of an electrical circuit in a package may be adjusted to a predetermined value by changes in the dielectric structure between two levels of circuitry.This adjustment in the composite dielectric structure is accomplished by changes in the electrical properties of the composite dielectric material, one level being preset to a value and the other level being adjusted by alterations of predetermined amounts that depend upon the performance desired.
摘要翻译：本公开描述了一种技术，其中通过两级电路之间的电介质结构的改变，可以将封装中的电路的电特性调整到预定值。复合电介质结构中的这种调整是通过复合电介质材料的电性能的变化来实现的，一个电平被预设为一个值，另一个电平通过依赖于期望性能的预定量的改变来调节。

4. 发明授权

US06269327B1 System and method for generating wire bond fingers 失效
标题翻译：用于生成电线键合指的系统和方法
公开(公告)号：US06269327B1
公开(公告)日：2001-07-31
申请号：US09248342
申请日：1999-02-11
申请人： Richard G. Bednar , Thomas P. Comino , Donald J. Malling , David P. Pagnani
发明人： Richard G. Bednar , Thomas P. Comino , Donald J. Malling , David P. Pagnani
IPC分类号： G06G748
CPC分类号： H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/49173 , H01L2224/49433 , H01L2224/78901 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01076 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Chip carrier topology including a plurality of bond lines radiating from a line of chip pads to at least one of zero or more finger lines and zero or more voltage lines is defined by first collecting topology parameters selected from the set including the number of rows of fingers; the spacing between rows of fingers; finger style, said finger style being one of arc-of-circle, constant-bond-length, and encompassing-rectangle; location of voltage rings; value of voltage rings; location of chip pads; voltage of chip pads; dimensions of output fingers; minimum finger pair spacing; maximum finger angle with respect to its bond line; minimum spacing of bond line terminations at voltage rings; and minimum spacing of bond line terminations with respect to and adjacent bond line which terminates at a finger. A plurality of possible topology solutions are generated, and a single possible topology solution selected for further processing. From the single possible solution, a topology solution is generated by placing a middle finger with respect to a middle chip pad, processing alternative chip pads to the right and left sequentially from the middle chip pad selectively to position ring intercepts, inner row fingers and outer row fingers. The topology solution thus generated is evaluated and if acceptable, the result is output to an output file; if not acceptable for failure to conform to all topology parameters, the topology parameters are adjusted and the topology solution generated anew.
摘要翻译：通过首先收集从包括手指的行数的集合中选择的拓扑参数来定义包括从芯片焊盘线发射到零个或多个指状线和零个或多个电压线中的至少一个的多个键合线的芯片载体拓扑 ; 手指排之间的间距; 手指风格，指的是圆弧，恒定键长度和包围矩形之一; 电压环位置; 电压环值; 芯片贴片位置; 芯片焊盘电压; 输出手指的尺寸; 最小手指对间距; 相对于其粘合线的最大指角; 电压环上键合线终端的最小间距; 并且相对于终止于手指的结合线和相邻键合线的终止点的最小间距。生成多种可能的拓扑解决方案，并选择一种可能的拓扑解决方案进行进一步处理。从单一可能的解决方案中，通过相对于中间芯片焊盘放置中指产生拓扑解决方案，从中间芯片焊盘选择性地顺序地向左右依次地处理替代的芯片焊盘以定位环截距，内部行指和外部行指。对如此生成的拓扑解决方案进行评估，如果可以接受，则将结果输出到输出文件; 如果不符合所有拓扑参数的可接受性，则调整拓扑参数，并重新生成拓扑解。

5. 发明授权

US5239289A Tunable inductor 失效
标题翻译：可调电感
公开(公告)号：US5239289A
公开(公告)日：1993-08-24
申请号：US754856
申请日：1991-09-04
申请人： Frank D. Ferraiolo , David P. Pagnani , Peter R. Tomaszewski
发明人： Frank D. Ferraiolo , David P. Pagnani , Peter R. Tomaszewski
IPC分类号： H01F17/00
CPC分类号： H01F17/0006
摘要： A compact, wide range inductor capable of being trimmed to a desired frequency value, comprising at least two individually tunable inductive elements of different resolution, disposed upon an insulative support. The inductor is usually placed within a hybrid circuit and trimmed after component population.
摘要翻译：一种紧凑的宽范围电感器，其能够被修剪到期望的频率值，包括设置在绝缘支撑上的至少两个具有不同分辨率的可单独调谐的感应元件。电感通常放置在混合电路中，并在组件总数之后进行修整。

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