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1. 发明申请

US20160099341A1 HIGH BREAKDOWN VOLTAGE LDMOS DEVICE 有权
标题翻译：高电压LDMOS器件
公开(公告)号：US20160099341A1
公开(公告)日：2016-04-07
申请号：US14968343
申请日：2015-12-14
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

2. 发明授权

US09306060B1 Semiconductor devices and related fabrication methods 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US09306060B1
公开(公告)日：2016-04-05
申请号：US14548616
申请日：2014-11-20
申请人： Hongning Yang , Daniel J. Blomberg , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7823 , H01L21/26513 , H01L29/0623 , H01L29/0634 , H01L29/0646 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/66689 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的半导体材料的主体区域，在体区内具有第二导电类型的半导体材料的源极区域，具有第二导电类型的半导体材料的结隔离区域，漏极区域具有第二导电类型的半导体材料以及具有第二导电类型的半导体材料的第一和第二漂移区。第一漂移区域横向地位于漏极区域和结隔离区域之间，结隔离区域横向位于第一漂移区域和第二漂移区域之间，并且第二漂移区域横向居住在体区域和结隔离区域之间。

3. 发明授权

US09059008B2 Resurf high voltage diode 有权
标题翻译： Resurf高压二极管
公开(公告)号：US09059008B2
公开(公告)日：2015-06-16
申请号：US13656103
申请日：2012-10-19
申请人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/739
CPC分类号： H01L29/063 , H01L29/0649 , H01L29/0692 , H01L29/66356 , H01L29/7391 , H01L29/861
摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
摘要翻译：提供了沟槽隔离的RESURF二极管结构（100），其包括衬底（150），其中形成阳极（130,132）和阴极（131）的接触区域，所述接触区域通过浅沟槽隔离区域（114,115）），以及形成在RESURF阳极延伸区域（106,107）下方的掩埋阴极延伸区域（104），使得阴极延伸区域（104）延伸超出阴极接触（131）以夹在上部和下部区域之间 103,106,107）。

4. 发明申请

US20150097265A1 Semiconductor Device with Buried Conduction Path 有权
标题翻译：具有埋地导电路径的半导体器件
公开(公告)号：US20150097265A1
公开(公告)日：2015-04-09
申请号：US14047222
申请日：2013-10-07
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/735 , H01L29/66
CPC分类号： H01L29/6625 , H01L21/26513 , H01L21/266 , H01L21/76224 , H01L29/0649 , H01L29/08 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/735
摘要： A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.
摘要翻译：一种器件包括设置在半导体衬底中的半导体衬底，发射极和集电极区域，具有第一导电类型并且彼此横向间隔开;以及复合衬底区域，设置在半导体衬底中，具有第二导电类型，并且包括基极接触区域，在工作期间形成发射极和集电极区域之间的掩埋传导路径的埋入区域和电连接基极接触区域和埋入区域的基极连接区域。基极区域的掺杂剂浓度水平高于掩埋区域，并且横向设置在发射极和集电极区域之间。

5. 发明授权

US08946860B2 Semiconductor device and related fabrication methods 有权
公开(公告)号：US08946860B2
公开(公告)日：2015-02-03
申请号：US13773432
申请日：2013-02-21
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/73 , H01L29/66 , H01L29/732 , H01L29/36 , H01L29/06
CPC分类号： H01L29/6625 , H01L21/265 , H01L29/0649 , H01L29/36 , H01L29/66234 , H01L29/66272 , H01L29/73 , H01L29/732 , H01L29/735
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

6. 发明授权

US08847358B2 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US08847358B2
公开(公告)日：2014-09-30
申请号：US13590411
申请日：2012-08-21
申请人： Xin Lin , Daniel J Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/6625 , H01L21/74 , H01L29/0821 , H01L29/66265 , H01L29/7317 , H01L29/735
摘要： A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.
摘要翻译：具有上表面的双极晶体管包括形成在相反导电类型的基极区域中并且具有耦合到集电极触点的第一垂直范围的第一部分的多电平集电结构，相邻的第二部分具有第二垂直范围第三部分第三垂直范围并且期望地具有与第二部分的深度不同的深度，通过第四部分耦合到第二部分，期望地具有小于第三垂直范围的第四垂直范围。第一基部区域部分覆盖在第二部分上，第二基部区域部分将第三部分与上覆的基部接触区域分开，并且其他基部区域部分横向地围绕并位于多层收集器结构之下。靠近上表面的发射体与多层收集器结构横向间隔开。该组合提供改善的增益，早期电压和击穿电压。

7. 发明申请

US20140134820A1 METHODS FOR PRODUCING BIPOLAR TRANSISTORS WITH IMPROVED STABILITY 有权
标题翻译：用于生产具有改进的稳定性的双极晶体管的方法
公开(公告)号：US20140134820A1
公开(公告)日：2014-05-15
申请号：US14157317
申请日：2014-01-16
申请人： XIN LIN , DANIEL J. BLOMBERG , HONGNING YANG , JIANG-KAI ZUO
发明人： XIN LIN , DANIEL J. BLOMBERG , HONGNING YANG , JIANG-KAI ZUO
IPC分类号： H01L29/66
CPC分类号： H01L29/6625 , H01L21/82285 , H01L27/0826 , H01L29/735
摘要： Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
摘要翻译：通过提供与晶体管表面上的发射极相同的导电类型的另外的掺杂区域，可以减少或消除具有延伸到发射极和基极接触之间的晶体管表面的基极的一部分的双极晶体管中的不稳定性和漂移在发射极和基极之间。另外的区域期望比表面上的基极区域重掺杂，并且比相邻的发射极更重掺杂。在另一个实施例中，与发射器相同的导电类型的仍然还是另外的区域被提供在另外的区域和发射极之间或者在发射极内侧。仍然还是进一步的区域期望比其他区域更重掺杂。这样的另外的区域屏蔽近表面碱基区域可能存在于覆盖晶体管表面的电介质层或界面中的俘获电荷。

8. 发明授权

US08669640B2 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US08669640B2
公开(公告)日：2014-03-11
申请号：US12502812
申请日：2009-07-14
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/735 , H01L21/331
CPC分类号： H01L29/66234 , H01L27/082 , H01L29/0692 , H01L29/0821 , H01L29/1004 , H01L29/73 , H01L29/7322
摘要： An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30). The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.
摘要翻译：提供了一种改进的装置（20），包括合并的垂直（251）和横向晶体管（252），其包括夹在相对的上部（362）和下部（30）底部区域之间的第一导电类型的集电极区域（34）导电类型通过相同导电类型的中间区域（32,361）和基极触点（38）经欧姆耦合。发射极（40）设置在上部基极区域（362）中，并且集电极触点（42）设置在延伸到薄的集电极区域（34）和下面的埋层（28）的外部沉降片区域（28）中。当集电极电压增加时，薄集电极区域（34）的一部分从上部（362）从顶部变成载流子，而从底部减少下部（30）的基极区域。这样使得集电极区域（34）的电压远低于形成在掩埋层（28）和下部基极区域（30）之间的PN结的击穿电压。增益和早期电压增加和解耦，并获得更高的击穿电压。

9. 发明申请

US20130149831A1 METHODS FOR FABRICATING BIPOLAR TRANSISTORS WITH IMPROVED GAIN 有权
标题翻译：用改进增益制备双极晶体管的方法
公开(公告)号：US20130149831A1
公开(公告)日：2013-06-13
申请号：US13760882
申请日：2013-02-06
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/66234 , H01L29/0821 , H01L29/41708 , H01L29/66272 , H01L29/732
摘要： Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE≧CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
摘要翻译：通过提供小于总发射极（42）区域的合金化（例如硅化物）发射极接触（452），双极晶体管（20）的增益不足得到改善。改进的发射极（42）具有第一掺杂浓度CFE的第一发射极（FE）部分（42-1）和第二掺杂浓度CSE的第二发射极（SE）部分（42-2）。优选CSE> = CFE。 SE部分（42-2）理想地包括与FE部分（42-1）的多个子区域（47m，47n，47p）混合的多个子区域（45i，45j，45k）。理想地，将半导体 - 金属合金或化合物（例如，硅化物）用于与SE部分（42-2）的欧姆接触（452），但基本上不用于FE部分（42-1）。包括电耦合到SE部分（42-2）但基本上不接触SE部分（42-2）上的发射极触点（452）的FE部分（42-1）提供多达〜278的增益。

10. 发明授权

US08134219B2 Schottky diodes 有权
标题翻译：肖特基二极管
公开(公告)号：US08134219B2
公开(公告)日：2012-03-13
申请号：US13150831
申请日：2011-06-01
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07 , H01L31/108
CPC分类号： H01L29/808 , H01L29/0619 , H01L29/66143 , H01L29/66901 , H01L29/806 , H01L29/872
摘要： Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.
摘要翻译：通过以串联位于包括肖特基接触和第二端子的第一端子之间的第一导电类型的电流路径构建JFET来提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管。电流通路是（i）在肖特基接触的基本上横向外侧的第二相对导电类型的多个基本上平行的手指区域之间，以及（ii）部分地位于第二导电类型的掩埋区域之下，路径，哪些区域电耦合到第一端子和肖特基接触，哪个部分电耦合到第二端子。当对第一端子和肖特基触点施加反向偏压时，电流路径在垂直或水平方向或两者上基本上被夹断，从而减小漏电流并提高器件的击穿电压。

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