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1. 发明授权

US5262351A Process for manufacturing a multilayer integrated circuit interconnection 失效
标题翻译：制造多层集成电路互连的方法
公开(公告)号：US5262351A
公开(公告)日：1993-11-16
申请号：US734671
申请日：1991-07-23
申请人： Jean-Marc Bureau , Francois Bernard , Dominique Broussoux , Claude Vergnolle
发明人： Jean-Marc Bureau , Francois Bernard , Dominique Broussoux , Claude Vergnolle
IPC分类号： H01L21/68 , H01L23/538 , H01L25/065 , H01L21/28 , H01L21/56 , H01L21/58 , H01L21/60
CPC分类号： H01L21/6835 , H01L23/5383 , H01L25/0652 , H01L2221/68359 , H01L2224/16225 , H01L2924/01014 , H01L2924/09701 , H01L2924/1627 , H01L2924/3025 , Y10S438/98
摘要： The invention is a method of producing a multilayer polymer-metal system to interconnect integrated circuits which allows two-dimensional electrical and/or optical connections between components, in which a first layer of polymer is deposited on a rigid substrate such that the layer can be separated from the substrate, in which a multilayer interconnection system is then produced on this first layer using industrial methods and in which the rigid substrate is removed after installation and connection of the integrated circuit.
摘要翻译：本发明是一种生产多层聚合物金属系统以互连集成电路的方法，其允许组件之间的二维电和/或光学连接，其中第一层聚合物沉积在刚性基底上，使得该层可以与衬底分离，其中使用工业方法在该第一层上制造多层互连系统，并且其中在安装和连接集成电路之后去除刚性衬底。

2. 发明授权

US5283851A Optical interconnection strip 失效
标题翻译：光互连条
公开(公告)号：US5283851A
公开(公告)日：1994-02-01
申请号：US947797
申请日：1992-09-21
申请人： Claude Vergnolle
发明人： Claude Vergnolle
IPC分类号： G02B6/42 , G02B6/28 , G02B6/43 , G02B6/44 , H01L31/0232 , H05K7/14
CPC分类号： G02B6/444 , G02B6/28 , G02B6/43
摘要： The strip is designed to optically interconnect a set of printed circuit boards mounted in a housing. It comprises:a U-section (29) lying alongside and against the edge of the set of printed circuit boards with its back (30) turned towards the printed circuit boards and including two lateral flanges, the back containing apertures (39, . . . , 44) drilled at the same pitch as the spacing of the printed circuit boards andoptical fibers (37, 38) laid in the section (29), running from one aperture (39, . . . , 44) to another, each aperture (39, . . . , 44) drilled in the back (30) of the said section (29) and containing one or several optical fiber (37, 38) ends lying opposite an optical half-connector mounted on the edge of one of the printed circuit boards.
摘要翻译：该条被设计成将安装在外壳中的一组印刷电路板光学互连。它包括：U形部分（29），其沿着该组印刷电路板的边缘并靠近该组印刷电路板的边缘，其背面（30）转向印刷电路板并且包括两个侧向凸缘，所述后部包含孔（39，...）以与放置在部分（29）中的印刷电路板和光纤（37,38）的间隔相同的间距钻出，从一个孔（39，...，44）延伸到另一个孔在所述部分（29）的后部（30）中钻出并且包含一个或多个光纤（37,38）的光阑（39，...，44），其端部与安装在所述部分（29）的边缘上的光学半连接器相对的印刷电路板。

3. 发明授权

US4216444A Step adjustable attenuator 失效
标题翻译：步进可调衰减器
公开(公告)号：US4216444A
公开(公告)日：1980-08-05
申请号：US942195
申请日：1978-09-14
申请人： Claude Vergnolle , Christian Val
发明人： Claude Vergnolle , Christian Val
IPC分类号： H01L27/01 , H03H7/24 , H05K1/00 , H05K1/16 , H03H7/26
CPC分类号： H03H7/24 , H01L27/016 , H05K1/0286 , H05K1/167
摘要： A step adjustable attenuator comprising a silicon substrate on one face of which are deposited thin film-type resistors and electrical conductors by which the resistors are interconnected. Contact points are arranged at the periphery of the substrate and connected to the resistors. However, the attenuating sections are not interconnected on the substrate. A conductive pattern prepared from a conductive film forms finger-like leads of which inner portions are bonded to the contact points. By its shape, the pattern ensures the interconnections between the sections and forms two rows of outputs, one for the connections on the printed-circuit board on which is implanted the attenuator and the other being associated with displaceable straps enabling attenuation to be adjusted.
摘要翻译：一个阶梯可调衰减器，其包括硅衬底，其一面是沉积的薄膜型电阻器和电导体，电阻器通过该电导体相互连接。接触点布置在基板的周边并连接到电阻器。然而，衰减部分不在衬底上互连。由导电膜制成的导电图案形成指状的引线，其内部部分接合到接触点。通过其形状，该图案确保了部分之间的互连并形成两排输出，一个用于印刷电路板上的连接，其上植入衰减器，另一个与可移位带相关联，使得能够进行衰减。

4. 发明授权

US4005467A High-power field-effect transistor and method of making same 失效
标题翻译：大功率场效应晶体管及其制作方法
公开(公告)号：US4005467A
公开(公告)日：1977-01-25
申请号：US606946
申请日：1975-08-22
申请人： Claude Vergnolle
发明人： Claude Vergnolle
IPC分类号： H01L29/06 , H01L29/10 , H01L29/20 , H01L29/417 , H01L29/808 , H01L29/80
CPC分类号： H01L29/41758 , H01L29/0657 , H01L29/1066 , H01L29/20 , H01L29/808
摘要： A field-effect transistor designed for high-power operation has a P.sup.+ substrate, preferably of gallium arsenide, topped by an N layer which in turn is covered by a much thinner N.sup.+ film, the layer and film being bisected by a serpentine trench so as to form a pair of interdigitated comb-shaped N.sup.+ segments overlain by metallic deposits which constitute a source and a drain electrode. The trench, advantageously produced by ion bombardment which also has a passivating effect on the surface areas thus exposed, cuts deep enough into the N layer to leave a channel whose conductivity is controlled by a gate electrode substantially coextensive therewith on the opposite substrate face. The prismatic substrate body is peripherally bounded by a mesa flank which may be passivated by a deposit of low-melting glass.
摘要翻译：设计用于高功率操作的场效应晶体管具有优选为砷化镓的P +衬底，其被N层覆盖，N层又被更薄的N +膜覆盖，该层和膜被二等分通过蛇形沟槽形成由构成源电极和漏电极的金属沉积物覆盖的一对叉指的梳状N +段。通过离子轰击有利地产生的沟槽也对这样暴露的表面区域具有钝化作用，将深度足够深地切割到N层中，以留下通道，其导电性由在相对的基板面上与其基本上共同延伸的栅电极控制。棱柱基体在外围被台面侧面限制，可以通过低熔点玻璃的沉积物钝化。

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