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1. 发明申请

US20120139114A1 COPPER INTERCONNECT STRUCTURE HAVING A GRAPHENE CAP 有权
标题翻译：铜箔互连结构
公开(公告)号：US20120139114A1
公开(公告)日：2012-06-07
申请号：US12961251
申请日：2010-12-06
申请人： John Hongguang Zhang , Cindy Goldberg , Walter Kleemeier , Ronald Kevin Sampson
发明人： John Hongguang Zhang , Cindy Goldberg , Walter Kleemeier , Ronald Kevin Sampson
IPC分类号： H01L23/535 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.
摘要翻译：铜互连结构具有本征石墨烯盖，用于通过减少时间相关介质击穿（TDDB）故障并提供电迁移阻力来改善互连的后端（BEOL）可靠性。通过沉积工艺将碳原子选择性地沉积在互连结构的铜层上以形成石墨烯盖。石墨烯帽增加了铜的活化能，从而允许更高的电流密度和改善的铜的电迁移性。通过在铜上沉积石墨烯盖，电介质区域保持没有导体，因此，层间电介质区域内的电流泄漏减小，从而减少TDDB故障并增加互连结构的寿命。 TDDB故障的减少和提高的电迁移性提高了铜互连结构的BEOL可靠性。

2. 发明申请

US20120122373A1 PRECISE REAL TIME AND POSITION LOW PRESSURE CONTROL OF CHEMICAL MECHANICAL POLISH (CMP) HEAD 审中-公开
标题翻译：精确实时和位置化学机械抛光（CMP）头的低压控制
公开(公告)号：US20120122373A1
公开(公告)日：2012-05-17
申请号：US12946155
申请日：2010-11-15
申请人： John H. Zhang , Paul Ferreira , Cindy Goldberg
发明人： John H. Zhang , Paul Ferreira , Cindy Goldberg
IPC分类号： B24B49/04 , B24B49/08
CPC分类号： B24B37/005 , B24B37/042 , B24B37/105 , B24B49/04 , B24B49/08 , H01L22/26
摘要： A method and system for detecting and controller wafer surface pressure distribution. Detecting and controlling wafer surface pressure distribution comprises measuring in situ wafer uniformity of a wafer at a plurality of locations of the wafer; and in response to the measured wafer uniformity controlling through a feedback loop in situ CMP head pressure applied at the plurality of locations of the wafer in real time to polish the wafer.
摘要翻译：一种用于检测和控制晶片表面压力分布的方法和系统。检测和控制晶片表面压力分布包括在晶片的多个位置处测量晶片的原位晶片均匀性; 并且响应于通过在晶片的多个位置处施加的原位CMP头压力的反馈环控制测量的晶片均匀性来抛光晶片。

3. 发明授权

US07951729B2 Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereor, and material for coupling a dielectric layer and a metal layer in a semiconductor device 有权
标题翻译：包括耦合电介质层和金属层的半导体器件，其制造方法以及用于在半导体器件中耦合电介质层和金属层的材料
公开(公告)号：US07951729B2
公开(公告)日：2011-05-31
申请号：US12705038
申请日：2010-02-12
申请人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
发明人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3105 , C04B35/5603 , C04B35/565 , C04B2235/483 , C08G77/60 , C08L83/16 , C09D183/16 , H01L21/02063 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/288 , H01L21/76801 , H01L21/7682 , H01L21/76838
摘要： A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.
摘要翻译：一种钝化耦合材料，一方面使半导体器件中的电介质层钝化，另一方面，用于在随后的工艺步骤中允许或至少促进液相金属沉积。在具体实例中，电介质层可以是具有理想的降低介电常数k的多孔材料，并且钝化耦合材料提供空间屏蔽基团，其基本上阻止环境水分吸附和吸收到多孔介电层中。与金属沉积相比，钝化耦合材料还提供金属成核侧，用于促进金属沉积在液相中，而不存在钝化偶联材料。使用液相金属沉积工艺有助于随后的半导体器件的制造。在一个实例中，钝化偶联材料在其化学组成中具有多个Si原子，这有利地增加了材料的热稳定性。

4. 发明申请

US20080182379A1 Semiconductor Wafer With Low-K Dielectric Layer and Process For Fabrication Thereof 有权
标题翻译：具有低K电介质层的半导体晶片及其制造方法
公开(公告)号：US20080182379A1
公开(公告)日：2008-07-31
申请号：US11910054
申请日：2005-03-31
申请人： Brad Smith , Cindy Goldberg , Robert E. Jones
发明人： Brad Smith , Cindy Goldberg , Robert E. Jones
IPC分类号： H01L21/76
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/26 , H01L21/7682 , H01L21/76825 , H01L21/76829 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.
摘要翻译：为了提高包含低k电介质层的晶片的机械强度，形成低k电介质层以具有低介电常数的某些区域，其余部分具有较高的机械强度。较高强度的区域可以具有相对较高的介电常数值。可以进行介电材料的选择性紫外线固化，以便从期望具有低介电常数的区域排出致孔剂。使用图案化以限定具有较低介电常数的区域的光掩模，硬掩模或不透明抗蚀剂来屏蔽电介质材料的剩余部分与紫外线辐射。或者，电介质材料层可以被覆盖固化以降低其介电常数，然后其非临界区域可以选择性地过度固化，从而产生增加的机械强度的区域。

5. 发明申请

US20130218316A1 ENDPOINT DETECTOR FOR A SEMICONDUCTOR PROCESSING STATION AND ASSOCIATED METHODS 有权
标题翻译：用于半导体加工站和相关方法的端点检测器
公开(公告)号：US20130218316A1
公开(公告)日：2013-08-22
申请号：US13401295
申请日：2012-02-21
申请人： John H. ZHANG , Cindy GOLDBERG
发明人： John H. ZHANG , Cindy GOLDBERG
IPC分类号： G06F19/00 , H01L21/306
CPC分类号： B24B37/013 , B24B49/12 , H01L22/12 , H01L22/26
摘要： A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.
摘要翻译：半导体处理装置包括半导体晶片的半导体处理站和与半导体处理站相关联的端点检测器。端点检测器包括配置成探测半导体晶片的非接触探针，被配置为将光信号传输到非接触探针的光发射器，以及被配置为从非接触探针接收反射光信号的光接收器。控制器基于反射光信号控制半导体处理站。

6. 发明授权

US07994069B2 Semiconductor wafer with low-K dielectric layer and process for fabrication thereof 有权
标题翻译：具有低K电介质层的半导体晶片及其制造方法
公开(公告)号：US07994069B2
公开(公告)日：2011-08-09
申请号：US11910054
申请日：2005-03-31
申请人： Brad Smith , Cindy Goldberg , Robert E. Jones
发明人： Brad Smith , Cindy Goldberg , Robert E. Jones
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/26 , H01L21/7682 , H01L21/76825 , H01L21/76829 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.
摘要翻译：为了提高包含低k电介质层的晶片的机械强度，形成低k电介质层以具有低介电常数的某些区域，其余部分具有较高的机械强度。较高强度的区域可以具有相对较高的介电常数值。可以进行介电材料的选择性紫外线固化，以便从期望具有低介电常数的区域排出致孔剂。使用图案化以限定具有较低介电常数的区域的光掩模，硬掩模或不透明抗蚀剂来屏蔽电介质材料的剩余部分与紫外线辐射。或者，电介质材料层可以被覆盖固化以降低其介电常数，然后其非临界区域可以选择性地过度固化，从而产生增加的机械强度的区域。

7. 发明授权

US09002493B2 Endpoint detector for a semiconductor processing station and associated methods 有权
标题翻译：半导体处理站端点检测器及相关方法
公开(公告)号：US09002493B2
公开(公告)日：2015-04-07
申请号：US13401295
申请日：2012-02-21
申请人： John H. Zhang , Cindy Goldberg
发明人： John H. Zhang , Cindy Goldberg
IPC分类号： G06F19/00 , B24B37/013 , B24B49/12 , H01L21/66
CPC分类号： B24B37/013 , B24B49/12 , H01L22/12 , H01L22/26
摘要： A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.
摘要翻译：半导体处理装置包括半导体晶片的半导体处理站和与半导体处理站相关联的端点检测器。端点检测器包括配置成探测半导体晶片的非接触探针，被配置为将光信号传输到非接触探针的光发射器，以及被配置为从非接触探针接收反射光信号的光接收器。控制器基于反射光信号控制半导体处理站。

8. 发明授权

US08476765B2 Copper interconnect structure having a graphene cap 有权
标题翻译：铜互连结构具有石墨烯盖
公开(公告)号：US08476765B2
公开(公告)日：2013-07-02
申请号：US12961251
申请日：2010-12-06
申请人： John Hongguang Zhang , Cindy Goldberg , Walter Kleemeier , Ronald Kevin Sampson
发明人： John Hongguang Zhang , Cindy Goldberg , Walter Kleemeier , Ronald Kevin Sampson
IPC分类号： H01L29/40 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.
摘要翻译：铜互连结构具有本征石墨烯盖，用于通过减少时间相关介质击穿（TDDB）故障并提供电迁移阻力来改善互连的后端（BEOL）可靠性。通过沉积工艺将碳原子选择性地沉积在互连结构的铜层上以形成石墨烯盖。石墨烯帽增加了铜的活化能，从而允许更高的电流密度和改善的铜的电迁移性。通过在铜上沉积石墨烯盖，电介质区域保持没有导体，因此层间电介质区域内的电流泄漏减小，从而减少TDDB故障并增加互连结构的寿命。 TDDB故障的减少和提高的电迁移性提高了铜互连结构的BEOL可靠性。

9. 发明授权

US07691756B2 Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and material for coupling a dielectric layer and a metal layer in a semiconductor device 有权
标题翻译：包括耦合电介质层和金属层的半导体器件，其制造方法以及用于在半导体器件中耦合电介质层和金属层的材料
公开(公告)号：US07691756B2
公开(公告)日：2010-04-06
申请号：US12065179
申请日：2006-09-01
申请人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
发明人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3105 , C04B35/5603 , C04B35/565 , C04B2235/483 , C08G77/60 , C08L83/16 , C09D183/16 , H01L21/02063 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/288 , H01L21/76801 , H01L21/7682 , H01L21/76838
摘要： A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.
摘要翻译：一种钝化耦合材料，一方面使半导体器件中的电介质层钝化，另一方面，用于在随后的工艺步骤中允许或至少促进液相金属沉积。在具体实例中，电介质层可以是具有理想的降低介电常数k的多孔材料，并且钝化耦合材料提供空间屏蔽基团，其基本上阻止环境水分吸附和吸收到多孔介电层中。与金属沉积相比，钝化耦合材料还提供金属成核侧，用于促进金属沉积在液相中，而不存在钝化偶联材料。使用液相金属沉积工艺有助于随后的半导体器件的制造。在一个实例中，钝化偶联材料在其化学组成中具有多个Si原子，这有利地增加了材料的热稳定性。

10. 发明申请

US20090134496A1 WAFER AND METHOD OF FORMING ALIGNMENT MARKERS 审中-公开
标题翻译：形成对齐标记的波形和方法
公开(公告)号：US20090134496A1
公开(公告)日：2009-05-28
申请号：US12305109
申请日：2006-07-06
申请人： Scott Warrick , Clyde Browning , Kevin Cooper , Cindy Goldberg , Brad Smith
发明人： Scott Warrick , Clyde Browning , Kevin Cooper , Cindy Goldberg , Brad Smith
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure.
摘要翻译：晶片包括多层结构。多层结构包括邻近用于接收对准标记的区域的第一装置结构。多个对准标记延伸到多层结构中并且位于用于接收对准标记的区域内。多个对准标记被布置成防止裂纹在发生时超过材料相关的临界长度在对应于用于接收对准结构的区域的多层结构的一部分中的传播。材料依赖的临界长度与多层结构的一部分相关联。

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