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1. 发明申请

US20120122373A1 PRECISE REAL TIME AND POSITION LOW PRESSURE CONTROL OF CHEMICAL MECHANICAL POLISH (CMP) HEAD 审中-公开
标题翻译：精确实时和位置化学机械抛光（CMP）头的低压控制
公开(公告)号：US20120122373A1
公开(公告)日：2012-05-17
申请号：US12946155
申请日：2010-11-15
申请人： John H. Zhang , Paul Ferreira , Cindy Goldberg
发明人： John H. Zhang , Paul Ferreira , Cindy Goldberg
IPC分类号： B24B49/04 , B24B49/08
CPC分类号： B24B37/005 , B24B37/042 , B24B37/105 , B24B49/04 , B24B49/08 , H01L22/26
摘要： A method and system for detecting and controller wafer surface pressure distribution. Detecting and controlling wafer surface pressure distribution comprises measuring in situ wafer uniformity of a wafer at a plurality of locations of the wafer; and in response to the measured wafer uniformity controlling through a feedback loop in situ CMP head pressure applied at the plurality of locations of the wafer in real time to polish the wafer.
摘要翻译：一种用于检测和控制晶片表面压力分布的方法和系统。检测和控制晶片表面压力分布包括在晶片的多个位置处测量晶片的原位晶片均匀性; 并且响应于通过在晶片的多个位置处施加的原位CMP头压力的反馈环控制测量的晶片均匀性来抛光晶片。

2. 发明授权

US09002493B2 Endpoint detector for a semiconductor processing station and associated methods 有权
标题翻译：半导体处理站端点检测器及相关方法
公开(公告)号：US09002493B2
公开(公告)日：2015-04-07
申请号：US13401295
申请日：2012-02-21
申请人： John H. Zhang , Cindy Goldberg
发明人： John H. Zhang , Cindy Goldberg
IPC分类号： G06F19/00 , B24B37/013 , B24B49/12 , H01L21/66
CPC分类号： B24B37/013 , B24B49/12 , H01L22/12 , H01L22/26
摘要： A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.
摘要翻译：半导体处理装置包括半导体晶片的半导体处理站和与半导体处理站相关联的端点检测器。端点检测器包括配置成探测半导体晶片的非接触探针，被配置为将光信号传输到非接触探针的光发射器，以及被配置为从非接触探针接收反射光信号的光接收器。控制器基于反射光信号控制半导体处理站。

3. 发明授权

US08569899B2 Device and method for alignment of vertically stacked wafers and die 有权
标题翻译：用于对准垂直堆叠的晶片和模具的装置和方法
公开(公告)号：US08569899B2
公开(公告)日：2013-10-29
申请号：US12650372
申请日：2009-12-30
申请人： John H. Zhang , Walter Kleemeier , Paul Ferreira , Ronald K. Sampson
发明人： John H. Zhang , Walter Kleemeier , Paul Ferreira , Ronald K. Sampson
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L22/14 , H01L22/22 , H01L22/34 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/1461 , H01L2924/00
摘要： A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
摘要翻译：提供了一种装置，其包括具有第一对准结构的第一管芯，所述第一对准结构包括布置成图案的多个第一传输柱和位于所述第一管芯上的第二管芯，所述第二管芯具有第二对准结构，所述第二对准结构包括多个第二传输列以与第一传输列相同的图案排列。第一和第二透射柱分别与第一和第二模具的第一表面和第二表面共面。

4. 发明授权

US08603916B2 CMP techniques for overlapping layer removal 有权
标题翻译：重叠层去除的CMP技术
公开(公告)号：US08603916B2
公开(公告)日：2013-12-10
申请号：US12649491
申请日：2009-12-30
申请人： John H. Zhang , Paul Ferreira
发明人： John H. Zhang , Paul Ferreira
IPC分类号： H01L21/302
CPC分类号： H01L21/823807 , H01L21/31053 , H01L29/7843
摘要： Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.
摘要翻译：化学机械抛光可用于平面化具有图案重叠层的半导体晶片。各向同性蚀刻可以去除图案重叠层的一部分以产生减小的高度的锥形侧壁。可以使用CMP去除重叠层的一部分。重叠层可以具有比下层更高的抛光速率，使得在去除覆盖层之后，下层保持基本完整。

5. 发明申请

US20110156152A1 CMP TECHNIQUES FOR OVERLAPPING LAYER REMOVAL 有权
标题翻译：用于覆盖层移除的CMP技术
公开(公告)号：US20110156152A1
公开(公告)日：2011-06-30
申请号：US12649491
申请日：2009-12-30
申请人： John H. Zhang , Paul Ferreira
发明人： John H. Zhang , Paul Ferreira
IPC分类号： H01L27/092 , H01L21/306
CPC分类号： H01L21/823807 , H01L21/31053 , H01L29/7843
摘要： Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.
摘要翻译：化学机械抛光可用于平面化具有图案重叠层的半导体晶片。各向同性蚀刻可以去除图案重叠层的一部分以产生减小的高度的锥形侧壁。可以使用CMP去除重叠层的一部分。重叠层可以具有比下层更高的抛光速率，使得在去除覆盖层之后，下层保持基本完整。

6. 发明申请

US20110156284A1 DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE 有权
标题翻译：垂直堆叠波形和垂直对准的装置和方法
公开(公告)号：US20110156284A1
公开(公告)日：2011-06-30
申请号：US12650372
申请日：2009-12-30
申请人： John H. Zhang , Walter Kleemeier , Paul Ferreira , Ronald K. Sampson
发明人： John H. Zhang , Walter Kleemeier , Paul Ferreira , Ronald K. Sampson
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L23/544 , H01L22/14 , H01L22/22 , H01L22/34 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/1461 , H01L2924/00
摘要： A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
摘要翻译：提供了一种装置，其包括具有第一对准结构的第一管芯，所述第一对准结构包括布置成图案的多个第一传输柱和位于所述第一管芯上的第二管芯，所述第二管芯具有第二对准结构，所述第二对准结构包括多个第二传输列以与第一传输列相同的图案排列。第一和第二透射柱分别与第一和第二模具的第一表面和第二表面共面。

7. 发明授权

US08921976B2 Using backside passive elements for multilevel 3D wafers alignment applications 有权
标题翻译：使用背面无源元件进行多层次3D晶圆校准应用
公开(公告)号：US08921976B2
公开(公告)日：2014-12-30
申请号：US13324791
申请日：2011-12-13
申请人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
发明人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
IPC分类号： H01L27/08 , H01L25/00 , H01L25/065 , H01L27/06 , H01L23/64 , H01L23/00
CPC分类号： H01L27/0694 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2223/6677 , H01L2224/02372 , H01L2224/0401 , H01L2224/05547 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2224/2919 , H01L2224/32145 , H01L2224/80357 , H01L2224/80805 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/01029 , H01L2924/01322 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/014 , H01L2924/00
摘要： Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.
摘要翻译：无源电路元件形成在两个集成电路晶片的表面。无源电路元件用于对准两个集成电路晶片以形成集成电路晶片叠层。

8. 发明申请

US20140080304A1 INTEGRATED TOOL FOR SEMICONDUCTOR MANUFACTURING 审中-公开
标题翻译：集成工具用于半导体制造
公开(公告)号：US20140080304A1
公开(公告)日：2014-03-20
申请号：US13619507
申请日：2012-09-14
申请人： John H. Zhang
发明人： John H. Zhang
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/677
CPC分类号： H01L21/67219 , H01L21/67167 , H01L21/67184
摘要： An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process.
摘要翻译：一种集成的工具，通过减少制造过程中的队列时间来减少制造半导体器件的缺陷。该集成工具可以包括至少一个抛光工具，其包括至少一个抛光模块和至少一个沉积工具，其包括至少一个沉积室。至少一个抽水室可以将抛光工具连接到沉积工具。所述至少一个排水室包括半导体器件通过的通道。通过在制造过程的各个阶段减少队列时间来减少半导体器件中的缺陷。

9. 发明申请

US20140080229A1 ADAPTIVE SEMICONDUCTOR PROCESSING USING FEEDBACK FROM MEASUREMENT DEVICES 审中-公开
标题翻译：使用来自测量装置的反馈的自适应半导体处理
公开(公告)号：US20140080229A1
公开(公告)日：2014-03-20
申请号：US13619722
申请日：2012-09-14
申请人： John H. Zhang
发明人： John H. Zhang
IPC分类号： H01L21/66
CPC分类号： B24B7/228 , B24B37/005 , B24B49/04 , B24B49/105
摘要： A semiconductor processing device and a method of operating the same. The method may include measuring at least one property of a semiconductor wafer and determining a recipe for processing the semiconductor wafer based on the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules based on the determined recipe, wherein the recipe comprises a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an inline metrology device. The recipe and various parameters associated with the recipe may be determined by a controller of the semiconductor processing device.
摘要翻译：一种半导体处理装置及其操作方法。该方法可以包括测量半导体晶片的至少一个性质并且基于至少一个特性确定用于处理半导体晶片的配方。可以基于所确定的配方，利用多个化学机械抛光（CMP）模块来处理半导体晶片，其中所述配方包括用于所述多个CMP模块中的每一个的至少一个参数的值。测量可以在原位或通过在线测量装置进行。配方和与配方相关的各种参数可以由半导体处理装置的控制器确定。

10. 发明申请

US20120168958A1 METHOD AND SYSTEM FOR FORMING DUMMY STRUCTURES IN ACCORDANCE WITH THE GOLDEN RATIO 有权
标题翻译：根据黄金比例形成DUMMY结构的方法和系统
公开(公告)号：US20120168958A1
公开(公告)日：2012-07-05
申请号：US12982784
申请日：2010-12-30
申请人： John H. Zhang , Heng Yang
发明人： John H. Zhang , Heng Yang
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/3212 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.
摘要翻译：本公开涉及根据黄金比率形成假结构以减少化学机械抛光期间的凹陷和侵蚀的方法。该方法包括在化学机械平面化之前确定模具的至少一个未填充部分并且用多个虚拟结构填充至少一个未填充部分，虚拟结构与未填充部分的总面积的比率在范围为36％和39％。根据该方法形成的管芯可以包括多个金属层和在每个金属层处的多个区域，每个区域具有形成为金色矩形的多个虚拟结构。

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